diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 9a01eb87bfb..ec3d2b50a9e 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -10,6 +10,7 @@
 #ifndef TCG_CPU_OPS_H
 #define TCG_CPU_OPS_H
 
+#include "qemu/arch_id.h"
 #include "exec/breakpoint.h"
 #include "exec/hwaddr.h"
 #include "exec/memattrs.h"
@@ -18,6 +19,8 @@
 #include "exec/vaddr.h"
 
 struct TCGCPUOps {
+    QemuArch arch_id;
+
     /**
      * @initialize_once: Initialize TCG state
      *
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 4a20b0c5d16..e020b4ce173 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -220,6 +220,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps alpha_tcg_ops = {
+    .arch_id = QEMU_ARCH_ALPHA,
     .initialize_once = alpha_translate_init,
     .synchronize_from_tb = alpha_cpu_synchronize_from_tb,
     .restore_state_to_opc = alpha_restore_state_to_opc,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f5b0c33a6dc..9b088c893bf 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2671,6 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
 
 #ifdef CONFIG_TCG
 static const TCGCPUOps arm_tcg_ops = {
+    .arch_id = QEMU_ARCH_ARM,
     .initialize_once = arm_translate_init,
     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
     .debug_excp_handler = arm_debug_excp_handler,
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 7a887a29b75..7a316561acc 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -233,6 +233,7 @@ static void cortex_m55_initfn(Object *obj)
 }
 
 static const TCGCPUOps arm_v7m_tcg_ops = {
+    .arch_id = QEMU_ARCH_ARM,
     .initialize_once = arm_translate_init,
     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
     .debug_excp_handler = arm_debug_excp_handler,
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index e69b5a6af9b..a9cce351755 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -206,6 +206,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps avr_tcg_ops = {
+    .arch_id = QEMU_ARCH_AVR,
     .initialize_once = avr_cpu_tcg_init,
     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
     .restore_state_to_opc = avr_restore_state_to_opc,
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 6f7777c607e..2a3b2e5fb4f 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -322,6 +322,7 @@ static void hexagon_cpu_init(Object *obj)
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps hexagon_tcg_ops = {
+    .arch_id = QEMU_ARCH_HEXAGON,
     .initialize_once = hexagon_translate_init,
     .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
     .restore_state_to_opc = hexagon_restore_state_to_opc,
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e654f133636..9bee8ef24f6 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -221,6 +221,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps hppa_tcg_ops = {
+    .arch_id = QEMU_ARCH_HPPA,
     .initialize_once = hppa_translate_init,
     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
     .restore_state_to_opc = hppa_restore_state_to_opc,
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index b44d2f370d1..0577d6237a9 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -107,6 +107,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps x86_tcg_ops = {
+    .arch_id = QEMU_ARCH_I386,
     .initialize_once = tcg_x86_init,
     .synchronize_from_tb = x86_cpu_synchronize_from_tb,
     .restore_state_to_opc = x86_restore_state_to_opc,
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 32aa5468ceb..96ae8c4ef05 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -793,6 +793,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps loongarch_tcg_ops = {
+    .arch_id = QEMU_ARCH_LOONGARCH,
     .initialize_once = loongarch_translate_init,
     .synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
     .restore_state_to_opc = loongarch_restore_state_to_opc,
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 230057b7375..8a45fbe9d2f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -546,6 +546,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps m68k_tcg_ops = {
+    .arch_id = QEMU_ARCH_M68K,
     .initialize_once = m68k_tcg_init,
     .restore_state_to_opc = m68k_restore_state_to_opc,
 
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f75e1cf5ab1..e2cfbbbbefd 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -420,6 +420,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps mb_tcg_ops = {
+    .arch_id = QEMU_ARCH_MICROBLAZE,
     .initialize_once = mb_tcg_init,
     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
     .restore_state_to_opc = mb_restore_state_to_opc,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4f7d9c03599..769f25551c7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -551,6 +551,7 @@ static Property mips_cpu_properties[] = {
  * mips hardware (see hw/mips/jazz.c).
  */
 static const TCGCPUOps mips_tcg_ops = {
+    .arch_id = QEMU_ARCH_MIPS,
     .initialize_once = mips_tcg_init,
     .synchronize_from_tb = mips_cpu_synchronize_from_tb,
     .restore_state_to_opc = mips_restore_state_to_opc,
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 24125eea1e7..ac041b4427b 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -232,6 +232,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps openrisc_tcg_ops = {
+    .arch_id = QEMU_ARCH_OPENRISC,
     .initialize_once = openrisc_translate_init,
     .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
     .restore_state_to_opc = openrisc_restore_state_to_opc,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 9f90de7f6bd..13295b9dfcb 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7416,6 +7416,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps ppc_tcg_ops = {
+    .arch_id = QEMU_ARCH_PPC,
     .initialize_once = ppc_translate_init,
     .restore_state_to_opc = ppc_restore_state_to_opc,
 #ifdef CONFIG_USER_ONLY
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 2be43b90908..ad00183a830 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -133,6 +133,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
 }
 
 static const TCGCPUOps riscv_tcg_ops = {
+    .arch_id = QEMU_ARCH_RISCV,
     .initialize_once = riscv_translate_init,
     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
     .restore_state_to_opc = riscv_restore_state_to_opc,
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7c338b584e8..12ed4a4101f 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -192,6 +192,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps rx_tcg_ops = {
+    .arch_id = QEMU_ARCH_RX,
     .initialize_once = rx_translate_init,
     .synchronize_from_tb = rx_cpu_synchronize_from_tb,
     .restore_state_to_opc = rx_restore_state_to_opc,
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index a5ab2a083b5..984cacce2d4 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -357,6 +357,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
 }
 
 static const TCGCPUOps s390_tcg_ops = {
+    .arch_id = QEMU_ARCH_S390X,
     .initialize_once = s390x_translate_init,
     .restore_state_to_opc = s390x_restore_state_to_opc,
 
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 75d6504293f..cd7336bd7f2 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -247,6 +247,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps superh_tcg_ops = {
+    .arch_id = QEMU_ARCH_SH4,
     .initialize_once = sh4_translate_init,
     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
     .restore_state_to_opc = superh_restore_state_to_opc,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index d803c329650..7e89c4033b2 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -927,6 +927,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps sparc_tcg_ops = {
+    .arch_id = QEMU_ARCH_SPARC,
     .initialize_once = sparc_tcg_init,
     .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
     .restore_state_to_opc = sparc_restore_state_to_opc,
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 19c583ed326..a8864955201 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -170,6 +170,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps tricore_tcg_ops = {
+    .arch_id = QEMU_ARCH_TRICORE,
     .initialize_once = tricore_tcg_init,
     .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
     .restore_state_to_opc = tricore_restore_state_to_opc,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 71c0a10ef0c..5d115328ffb 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -227,6 +227,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps xtensa_tcg_ops = {
+    .arch_id = QEMU_ARCH_XTENSA,
     .initialize_once = xtensa_translate_init,
     .debug_excp_handler = xtensa_breakpoint_handler,
     .restore_state_to_opc = xtensa_restore_state_to_opc,
