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Tue, 26 Nov 2024 06:01:09 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbedebfsm13436096f8f.100.2024.11.26.06.01.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 06:01:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Jiaxun Yang Subject: [PATCH v3 10/16] target/mips: Introduce decode tree bindings for nanoMIPS ISA Date: Tue, 26 Nov 2024 14:59:56 +0100 Message-ID: <20241126140003.74871-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126140003.74871-1-philmd@linaro.org> References: <20241126140003.74871-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce the nanoMIPS decodetree configs for the 16-bit, 32-bit and 48-bit instructions. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 3 +++ target/mips/tcg/nanomips16.decode | 8 ++++++++ target/mips/tcg/nanomips32.decode | 8 ++++++++ target/mips/tcg/nanomips48.decode | 8 ++++++++ target/mips/tcg/nanomips_translate.c | 15 +++++++++++++++ target/mips/tcg/nanomips_translate.c.inc | 16 ++++++++++++++++ target/mips/tcg/meson.build | 4 ++++ 7 files changed, 62 insertions(+) create mode 100644 target/mips/tcg/nanomips16.decode create mode 100644 target/mips/tcg/nanomips32.decode create mode 100644 target/mips/tcg/nanomips48.decode create mode 100644 target/mips/tcg/nanomips_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 2a079cb28d9..7fe34a1d891 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -224,6 +224,9 @@ bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn); +bool decode_isa_nanomips16(DisasContext *ctx, uint16_t insn); +bool decode_isa_nanomips32(DisasContext *ctx, uint32_t insn); +bool decode_isa_nanomips48(DisasContext *ctx, uint64_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode new file mode 100644 index 00000000000..81fdc68e98b --- /dev/null +++ b/target/mips/tcg/nanomips16.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode new file mode 100644 index 00000000000..9cecf1e13d3 --- /dev/null +++ b/target/mips/tcg/nanomips32.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode new file mode 100644 index 00000000000..696cc15607a --- /dev/null +++ b/target/mips/tcg/nanomips48.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 48-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c new file mode 100644 index 00000000000..335a32845ed --- /dev/null +++ b/target/mips/tcg/nanomips_translate.c @@ -0,0 +1,15 @@ +/* + * MIPS emulation for QEMU - nanoMIPS translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-nanomips16.c.inc" +#include "decode-nanomips32.c.inc" +#include "decode-nanomips48.c.inc" diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index e0a920bdb3a..5d021f01128 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -4480,6 +4480,22 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); ctx->opcode = opcode; + if (decode_isa_nanomips16(ctx, opcode)) { + return 2; + } + + opcode <<= 16; + opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); + if (decode_isa_nanomips32(ctx, opcode)) { + return 4; + } + + opcode <<= 16; + opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 4); + if (decode_isa_nanomips48(ctx, opcode)) { + return 6; + } + rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode)); diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index ca70769912c..f674819e6a8 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -4,6 +4,9 @@ gen = [ decodetree.process('micromips16.decode', extra_args: ['--decode=decode_isa_micromips16', '--insnwidth=16']), decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), + decodetree.process('nanomips16.decode', extra_args: ['--decode=decode_isa_nanomips16', '--insnwidth=16']), + decodetree.process('nanomips32.decode', extra_args: ['--decode=decode_isa_nanomips32']), + decodetree.process('nanomips48.decode', extra_args: ['--decode=decode_isa_nanomips48', '--insnwidth=48']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), @@ -24,6 +27,7 @@ mips_ss.add(files( 'mips16e_translate.c', 'msa_helper.c', 'msa_translate.c', + 'nanomips_translate.c', 'op_helper.c', 'rel6_translate.c', 'translate.c',