diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 94dd30216f5..9517e18eef9 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -175,8 +175,8 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm,
 /*
  * Address Computation and Large Constant Instructions
  */
-void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
-void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs);
+void gen_op_addr_add_tl(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
+void gen_op_addr_addi_tl(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs);
 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 667b20bccb8..ad688b9b23d 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1415,7 +1415,7 @@ int get_fp_bit(int cc)
 }
 
 /* Addresses computation */
-void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
+void gen_op_addr_add_tl(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
 {
     tcg_gen_add_tl(ret, arg0, arg1);
 
@@ -1426,7 +1426,7 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
 #endif
 }
 
-void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs)
+void gen_op_addr_addi_tl(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs)
 {
     tcg_gen_addi_tl(ret, base, ofs);
 
@@ -1952,7 +1952,7 @@ void gen_base_offset_addr_tl(DisasContext *ctx, TCGv addr, int base, int offset)
         gen_load_gpr_tl(addr, base);
     } else {
         tcg_gen_movi_tl(addr, offset);
-        gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
+        gen_op_addr_add_tl(ctx, addr, cpu_gpr[base], addr);
     }
 }
 
@@ -2075,14 +2075,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
         break;
     case OPC_LDPC:
         t1 = tcg_constant_tl(pc_relative_pc(ctx));
-        gen_op_addr_add(ctx, t0, t0, t1);
+        gen_op_addr_add_tl(ctx, t0, t0, t1);
         tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ);
         gen_store_gpr_tl(t0, rt);
         break;
 #endif
     case OPC_LWPC:
         t1 = tcg_constant_tl(pc_relative_pc(ctx));
-        gen_op_addr_add(ctx, t0, t0, t1);
+        gen_op_addr_add_tl(ctx, t0, t0, t1);
         tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL);
         gen_store_gpr_tl(t0, rt);
         break;
@@ -4135,7 +4135,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
     t0 = tcg_temp_new();
 
     gen_base_offset_addr_tl(ctx, t0, rs, offset);
-    gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+    gen_op_addr_add_tl(ctx, t0, cpu_gpr[rd], t0);
 
     switch (opc) {
     case OPC_GSLBX:
@@ -4150,7 +4150,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
     case OPC_GSLWX:
         gen_base_offset_addr_tl(ctx, t0, rs, offset);
         if (rd) {
-            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+            gen_op_addr_add_tl(ctx, t0, cpu_gpr[rd], t0);
         }
         tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
                            ctx->default_tcg_memop_mask);
@@ -4160,7 +4160,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
     case OPC_GSLDX:
         gen_base_offset_addr_tl(ctx, t0, rs, offset);
         if (rd) {
-            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+            gen_op_addr_add_tl(ctx, t0, cpu_gpr[rd], t0);
         }
         tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
                            ctx->default_tcg_memop_mask);
@@ -4170,7 +4170,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
     case OPC_GSLWXC1:
         gen_base_offset_addr_tl(ctx, t0, rs, offset);
         if (rd) {
-            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+            gen_op_addr_add_tl(ctx, t0, cpu_gpr[rd], t0);
         }
         fp0 = tcg_temp_new_i32();
         tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
@@ -4181,7 +4181,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
     case OPC_GSLDXC1:
         gen_base_offset_addr_tl(ctx, t0, rs, offset);
         if (rd) {
-            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+            gen_op_addr_add_tl(ctx, t0, cpu_gpr[rd], t0);
         }
         tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
                            ctx->default_tcg_memop_mask);
@@ -10550,7 +10550,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
     } else if (index == 0) {
         gen_load_gpr_tl(t0, base);
     } else {
-        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
+        gen_op_addr_add_tl(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
     }
     /*
      * Don't do NOP if destination is zero: we must perform the actual
@@ -11050,7 +11050,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
             TCGv tbase = tcg_temp_new();
 
             gen_load_gpr_tl(tbase, rt);
-            gen_op_addr_addi(ctx, btarget, tbase, offset);
+            gen_op_addr_addi_tl(ctx, btarget, tbase, offset);
         }
         break;
     default:
@@ -11253,7 +11253,7 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
     if (index != 0) {
         gen_load_gpr_tl(t1, index);
         tcg_gen_shli_tl(t1, t1, 2);
-        gen_op_addr_add(ctx, t0, t1, t0);
+        gen_op_addr_add_tl(ctx, t0, t1, t0);
     }
 
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
@@ -11338,7 +11338,7 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
     } else if (offset == 0) {
         gen_load_gpr_tl(t0, base);
     } else {
-        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
+        gen_op_addr_add_tl(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
     }
 
     switch (opc) {
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 69289bc13bb..fb7e6c8ddd9 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -980,7 +980,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
         tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
                            ctx->default_tcg_memop_mask);
         gen_store_gpr_tl(t1, rd);
-        gen_op_addr_addi(ctx, t0, t0, 4);
+        gen_op_addr_addi_tl(ctx, t0, t0, 4);
         tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
                            ctx->default_tcg_memop_mask);
         gen_store_gpr_tl(t1, rd + 1);
@@ -989,7 +989,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
         gen_load_gpr_tl(t1, rd);
         tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
                            ctx->default_tcg_memop_mask);
-        gen_op_addr_addi(ctx, t0, t0, 4);
+        gen_op_addr_addi_tl(ctx, t0, t0, 4);
         gen_load_gpr_tl(t1, rd + 1);
         tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
                            ctx->default_tcg_memop_mask);
@@ -1003,7 +1003,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
         tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
                            ctx->default_tcg_memop_mask);
         gen_store_gpr_tl(t1, rd);
-        gen_op_addr_addi(ctx, t0, t0, 8);
+        gen_op_addr_addi_tl(ctx, t0, t0, 8);
         tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
                            ctx->default_tcg_memop_mask);
         gen_store_gpr_tl(t1, rd + 1);
@@ -1012,7 +1012,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
         gen_load_gpr_tl(t1, rd);
         tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
                            ctx->default_tcg_memop_mask);
-        gen_op_addr_addi(ctx, t0, t0, 8);
+        gen_op_addr_addi_tl(ctx, t0, t0, 8);
         gen_load_gpr_tl(t1, rd + 1);
         tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
                            ctx->default_tcg_memop_mask);
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 754a5f7be4c..7af83e77280 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -131,7 +131,7 @@ static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
 {
     TCGv t1 = tcg_temp_new();
 
-    gen_op_addr_addi(ctx, t0, t0, -4);
+    gen_op_addr_addi_tl(ctx, t0, t0, -4);
     gen_load_gpr_tl(t1, regidx);
     tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
                        ctx->default_tcg_memop_mask);
@@ -283,7 +283,7 @@ static void gen_mips16_save(DisasContext *ctx,
         }
     }
 
-    gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
+    gen_op_addr_addi_tl(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
 }
 
 static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
@@ -292,7 +292,7 @@ static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
     TCGv t2 = tcg_temp_new();
 
     tcg_gen_movi_tl(t2, -4);
-    gen_op_addr_add(ctx, t0, t0, t2);
+    gen_op_addr_add_tl(ctx, t0, t0, t2);
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
                        ctx->default_tcg_memop_mask);
     gen_store_gpr_tl(t1, regidx);
@@ -306,7 +306,7 @@ static void gen_mips16_restore(DisasContext *ctx,
     int astatic;
     TCGv t0 = tcg_temp_new();
 
-    gen_op_addr_addi(ctx, t0, cpu_gpr[29], -framesize);
+    gen_op_addr_addi_tl(ctx, t0, cpu_gpr[29], -framesize);
 
     if (do_ra) {
         decr_and_load(ctx, 31, t0);
@@ -386,7 +386,7 @@ static void gen_mips16_restore(DisasContext *ctx,
         }
     }
 
-    gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
+    gen_op_addr_addi_tl(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
 }
 
 #if defined(TARGET_MIPS64)
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 950a4c23e70..2ad936c66d4 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1058,7 +1058,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
 
 static void gen_adjust_sp(DisasContext *ctx, int u)
 {
-    gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u);
+    gen_op_addr_addi_tl(ctx, cpu_gpr[29], cpu_gpr[29], u);
 }
 
 static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
@@ -2398,7 +2398,7 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
 
     /* calculate btarget */
     tcg_gen_shli_tl(t0, t0, 1);
-    gen_op_addr_add(ctx, btarget, tcg_constant_tl(ctx->base.pc_next + 4), t0);
+    gen_op_addr_add_tl(ctx, btarget, tcg_constant_tl(ctx->base.pc_next + 4), t0);
 
     /* branch completion */
     clear_branch_hflags(ctx);
@@ -2453,7 +2453,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
             TCGv tbase = tcg_temp_new();
 
             gen_load_gpr_tl(tbase, rt);
-            gen_op_addr_addi(ctx, btarget, tbase, offset);
+            gen_op_addr_addi_tl(ctx, btarget, tbase, offset);
         }
         break;
     default:
@@ -2617,7 +2617,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
             return;
         }
     }
-    gen_op_addr_add(ctx, t0, t0, t1);
+    gen_op_addr_add_tl(ctx, t0, t0, t1);
 
     switch (extract32(ctx->opcode, 7, 4)) {
     case NM_LBX:
@@ -3654,7 +3654,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
         case NM_ADDIUGP_W:
             if (rt != 0) {
                 offset = extract32(ctx->opcode, 0, 21);
-                gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], offset);
+                gen_op_addr_addi_tl(ctx, cpu_gpr[rt], cpu_gpr[28], offset);
             }
             break;
         case NM_LWGP:
@@ -3689,7 +3689,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             case NM_ADDIUGP48:
                 check_nms(ctx);
                 if (rt != 0) {
-                    gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], addr_off);
+                    gen_op_addr_addi_tl(ctx, cpu_gpr[rt], cpu_gpr[28], addr_off);
                 }
                 break;
             case NM_ADDIUPC48:
@@ -3921,7 +3921,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 break;
             case NM_ADDIUGP_B:
                 if (rt != 0) {
-                    gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], u);
+                    gen_op_addr_addi_tl(ctx, cpu_gpr[rt], cpu_gpr[28], u);
                 }
                 break;
             case NM_P_GP_LH:
