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Tue, 26 Nov 2024 05:16:13 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fad61b0sm13546159f8f.7.2024.11.26.05.16.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 05:16:13 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang Subject: [PATCH 04/13] target/mips: Rename gen_move_high32() -> gen_move_high32_tl() Date: Tue, 26 Nov 2024 14:15:36 +0100 Message-ID: <20241126131546.66145-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126131546.66145-1-philmd@linaro.org> References: <20241126131546.66145-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org MIPS gen_move_high32() takes a target-specific TCGv argument. Rename it as gen_move_high32_tl() to clarify, like other TCG core helpers. Mechanical change doing: $ sed -i -e 's/gen_move_high32/gen_move_high32_tl/' \ $(git grep -l gen_move_high32) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 2 +- target/mips/tcg/mxu_translate.c | 2 +- target/mips/tcg/translate.c | 14 +++++++------- target/mips/tcg/nanomips_translate.c.inc | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 6437180d891..90b8ac0e5b1 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -154,7 +154,7 @@ void check_cop1x(DisasContext *ctx); void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); void gen_move_low32_tl(TCGv ret, TCGv_i64 arg); -void gen_move_high32(TCGv ret, TCGv_i64 arg); +void gen_move_high32_tl(TCGv ret, TCGv_i64 arg); void gen_load_gpr_tl(TCGv t, int reg); void gen_store_gpr_tl(TCGv t, int reg); #if defined(TARGET_MIPS64) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index 94aa137cb25..20b8314b478 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -4386,7 +4386,7 @@ static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns) tcg_gen_add_i64(t3, t3, t2); } gen_move_low32_tl(t1, t3); - gen_move_high32(t0, t3); + gen_move_high32_tl(t0, t3); tcg_gen_mov_tl(cpu_HI[0], t0); tcg_gen_mov_tl(cpu_LO[0], t1); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 5e776136f09..31907c75a62 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1462,7 +1462,7 @@ void gen_move_low32_tl(TCGv ret, TCGv_i64 arg) } /* Sign-extract the high 32-bits to a target_long. */ -void gen_move_high32(TCGv ret, TCGv_i64 arg) +void gen_move_high32_tl(TCGv ret, TCGv_i64 arg) { #if defined(TARGET_MIPS64) tcg_gen_sari_i64(ret, arg, 32); @@ -3342,7 +3342,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); } break; case OPC_MADDU: @@ -3358,7 +3358,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); } break; case OPC_MSUB: @@ -3372,7 +3372,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); } break; case OPC_MSUBU: @@ -3388,7 +3388,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); } break; default: @@ -3483,7 +3483,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); if (rd) { gen_move_low32_tl(cpu_gpr[rd], t2); } @@ -3505,7 +3505,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); if (rd) { gen_move_low32_tl(cpu_gpr[rd], t2); } diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 5a4a64f3609..b78381bcf54 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -1817,7 +1817,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); } break; case NM_MULT: @@ -1872,7 +1872,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); } break; case NM_MULTU: @@ -1933,7 +1933,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); } break; case NM_EXTRV_RS_W: @@ -1974,7 +1974,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); gen_move_low32_tl(cpu_LO[acc], t2); - gen_move_high32(cpu_HI[acc], t2); + gen_move_high32_tl(cpu_HI[acc], t2); } break; case NM_EXTRV_S_H: