@@ -41,11 +41,11 @@
#define R_TX_BUF0 0
#define BUFSZ_MAX 0x07e4
#define A_MDIO_BASE 0x07e4
-#define R_TX_LEN0 (0x07f4 / 4)
+#define A_TX_BASE0 0x07f4
#define R_TX_GIE0 (0x07f8 / 4)
#define R_TX_CTRL0 (0x07fc / 4)
#define R_TX_BUF1 (0x0800 / 4)
-#define R_TX_LEN1 (0x0ff4 / 4)
+#define A_TX_BASE1 0x0ff4
#define R_TX_CTRL1 (0x0ffc / 4)
#define R_RX_BUF0 (0x1000 / 4)
@@ -54,6 +54,11 @@
#define A_RX_BASE1 0x1ffc
#define R_MAX (0x2000 / 4)
+enum {
+ TX_LEN = 0,
+ TX_MAX
+};
+
enum {
RX_CTRL = 0,
RX_MAX
@@ -67,6 +72,7 @@ enum {
typedef struct XlnxXpsEthLitePort
{
+ MemoryRegion txio;
MemoryRegion rxio;
struct {
@@ -126,6 +132,52 @@ static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index)
return &s->regs[rxbase + R_RX_BUF0];
}
+static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ XlnxXpsEthLite *s = opaque;
+ unsigned port_index = addr_to_port_index(addr);
+ uint32_t r = 0;
+
+ switch (addr >> 2) {
+ case TX_LEN:
+ r = s->port[port_index].reg.tx_len;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ return r;
+}
+
+static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned int size)
+{
+ XlnxXpsEthLite *s = opaque;
+ unsigned port_index = addr_to_port_index(addr);
+
+ switch (addr >> 2) {
+ case TX_LEN:
+ s->port[port_index].reg.tx_len = value;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static const MemoryRegionOps eth_porttx_ops = {
+ .read = port_tx_read,
+ .write = port_tx_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size)
{
XlnxXpsEthLite *s = opaque;
@@ -190,11 +242,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
r = s->port[port_index].reg.tx_gie;
break;
- case R_TX_LEN0:
- case R_TX_LEN1:
- r = s->port[port_index].reg.tx_len;
- break;
-
case R_TX_CTRL1:
case R_TX_CTRL0:
r = s->port[port_index].reg.tx_ctrl;
@@ -240,11 +287,6 @@ eth_write(void *opaque, hwaddr addr,
break;
/* Keep these native. */
- case R_TX_LEN0:
- case R_TX_LEN1:
- s->port[port_index].reg.tx_len = value;
- break;
-
case R_TX_GIE0:
s->port[port_index].reg.tx_gie = value;
break;
@@ -333,6 +375,13 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0));
for (unsigned i = 0; i < 2; i++) {
+ memory_region_init_io(&s->port[i].txio, OBJECT(dev),
+ ð_porttx_ops, s,
+ i ? "ethlite.tx[1]io" : "ethlite.tx[0]io",
+ 4 * TX_MAX);
+ memory_region_add_subregion(&s->mmio, i ? A_TX_BASE1 : A_TX_BASE0,
+ &s->port[i].txio);
+
memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
ð_portrx_ops, s,
i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
Declare TX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007f7 (prio 0, i/o): ethlite.tx[0]io 00000000810007f8-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f8 0000000081000ff4-0000000081000ff7 (prio 0, i/o): ethlite.tx[1]io 0000000081000ff8-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ff8 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> --- hw/net/xilinx_ethlite.c | 73 ++++++++++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 12 deletions(-)