From patchwork Thu Nov 14 16:00:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 843136 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp359903wrc; Thu, 14 Nov 2024 08:03:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXKltAIAs76FAvDClPcMMrD0ot50cyTnTvmRSpsDv39USn3oKCE4BoPOnrDPlGaTI4ZNOwWLg==@linaro.org X-Google-Smtp-Source: AGHT+IGWJGhEksG5hYFq+bJSs4DWftsckv9XBzNf5wQoPx9x6fsmO25M9RU1aEeRmnXh0yAKUsFm X-Received: by 2002:a05:620a:4554:b0:7a7:f18a:e46f with SMTP id af79cd13be357-7b331f20b34mr3129654485a.43.1731600202060; Thu, 14 Nov 2024 08:03:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731600202; cv=none; d=google.com; s=arc-20240605; b=I0I5VkAeGFHnsvJV/4h1qy4JDBD3IJPskbAVGZ/E0Mf5d7ULQA2oNzE/bXyNOzQSfJ ef0vDGc4+YVPNWpbo9VKZMbaH3q+di3K0co1Gb7AG6gWIVkjgTaE5yqfKuKgP5inPZQX ziC6wDVtv1YEwRRpWmdkTTHNbPw9U0Y1v+QrZD7MrM7a0XZH02lgKEdaOMKVph0/sLXN 4lhObNp1jcbpxvLSRwpqK2GQ4WVAP8wZ7INDwIhf14X82jyR09Lu1/8BA3FKZJD43PeI TpDaYZc0hephPS79fhE5KRkP0iYm4oMn40wSzLd1f/eik41YxHTrleZHl1VkhI8/vsNA vEQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BsbKOlO+09+V06ilkiETtavIcLFq0cApuQcSVOlh0Qs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=LJ7b/tgH2JfFhfX7nkEgQXfxja7J6k+6zfNJTmLRPifYi2C+PWh/IZGwl8Q4DZN4N0 M/01tKGdDKUQOh3GMHYfJsl5M+jEe8xez0IAmSmR3o1V+eLReKHc9OktOebadQg3IMfQ R8ReGxDwYsOKmBmu6P4DGOFBmQWAzeua04jk8NcPG1S3OJwyvOHEP/bG2HBoxWy3jvaQ 4ASpGeUp8HJOV1cRTjsZwtKjjO/6TKpYFIRfpU6duhO5jLpGBcvi+QERJaYGU9v22gnf lUuyUPhU3eiDLXwjmHueKo95vu3aeeTpf3RtmyrcHtS9Ug7jPinpEiq+udmXspjM+wfv WQXw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AvxE0pze; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7b35ca2a0ccsi145562385a.213.2024.11.14.08.03.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Nov 2024 08:03:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AvxE0pze; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBcHz-0004xc-8g; Thu, 14 Nov 2024 11:01:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBcHt-0004va-V9 for qemu-devel@nongnu.org; Thu, 14 Nov 2024 11:01:42 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBcHs-0002C4-EJ for qemu-devel@nongnu.org; Thu, 14 Nov 2024 11:01:41 -0500 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-7eab7622b61so600731a12.1 for ; Thu, 14 Nov 2024 08:01:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731600099; x=1732204899; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BsbKOlO+09+V06ilkiETtavIcLFq0cApuQcSVOlh0Qs=; b=AvxE0pzeZrEsfZBXtJlQo7H5U0BUzJZnBTiSj6KhQGv2DLs1wWNxrzAtnbHE9oixJS RMKm+8zrDXtqtbsZyzZEDnpO+xtEHU06nrEuTECzkUXTwqoJw3pjr9boCX6468v/X/Qu aelmKQ28uDU49QddtuQr80yiGuKAtZ/hL0ZuoMcOh5mr7W7Xcp17Vi08I7VsnjbkyC5/ erk5BANyqRvFrd7nDjmLy9466xG0Z04XKXxrAllT3hivQYtklFJ1Se76XtGov5QMhv5C Dkb28ogIE1TodYQs4Ijk6G0k8Cd5Cpd2/vkZiq0lPt80jbsnyDI5mxzxj7XGBxLSOcmc Ksjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731600099; x=1732204899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BsbKOlO+09+V06ilkiETtavIcLFq0cApuQcSVOlh0Qs=; b=jvad674pSrUdPxH6ZjIOqmFpyb3JXoTDSCOIGcrc+EvRDa9l9EH0/NGDpDabGgkC1G 1tAi+jgbP02jp5IEIIrSKO1UVqX9FnkyhIpV1FMWeFvb04zD2uDqGJsX7X9IEjtYzufA ik2rl+93t/We9gygL1S3KYNbPIAypiMbupddigLFn8+5lwsRDY7b08IaezGbPuG6UBiV pZqsrJvP7DrzzllYRPR8zR3dClmro/U/9McA9E7RrKkq/EN2yC4Eod0yjm2hzMvY7q+X tjzdCuGBPClxZw7ULT+9RNE2Y8ta4383yfm6YOJSEzyQQ2EUJNc/YOtVqwLUXUWwijNA LOxQ== X-Gm-Message-State: AOJu0Yx6j8gUkX/k3IeGAnyd9a6Vx8l5X0+p3w+cehQqGG1FzdBi7/NP MnkSyghpPHNbH+HGXcbj+AoZts+4KjfCq/RZIsURuwZztjqIA7ZGcbZ5B8kvbe4Bqx7r+JjGFzG w X-Received: by 2002:a17:90b:2248:b0:2cd:4593:2a8e with SMTP id 98e67ed59e1d1-2e9b171ff77mr31886980a91.15.1731600098555; Thu, 14 Nov 2024 08:01:38 -0800 (PST) Received: from stoup.. ([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.01.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:01:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/54] accel/tcg: Flush entire tlb when a masked range wraps Date: Thu, 14 Nov 2024 08:00:44 -0800 Message-ID: <20241114160131.48616-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We expect masked address spaces to be quite large, e.g. 56 bits for AArch64 top-byte-ignore mode. We do not expect addr+len to wrap around, but it is possible with AArch64 guest flush range instructions. Convert this unlikely case to a full tlb flush. This can simplify the subroutines actually performing the range flush. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5510f40333..31c45a6213 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -802,6 +802,11 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, tlb_flush_page_by_mmuidx(cpu, addr, idxmap); return; } + /* If addr+len wraps in len bits, fall back to full flush. */ + if (bits < TARGET_LONG_BITS && ((addr ^ (addr + len - 1)) >> bits)) { + tlb_flush_by_mmuidx(cpu, idxmap); + return; + } /* This should already be page aligned */ d.addr = addr & TARGET_PAGE_MASK; @@ -838,6 +843,11 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); return; } + /* If addr+len wraps in len bits, fall back to full flush. */ + if (bits < TARGET_LONG_BITS && ((addr ^ (addr + len - 1)) >> bits)) { + tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, idxmap); + return; + } /* This should already be page aligned */ d.addr = addr & TARGET_PAGE_MASK;