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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9bab70sm1417926b3a.152.2024.11.14.08.05.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:05:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 54/54] accel/tcg: Return CPUTLBEntryTree from tlb_set_page_full Date: Thu, 14 Nov 2024 08:01:30 -0800 Message-ID: <20241114160131.48616-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Avoid a lookup to find the node that we have just inserted. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 20af48c6c5..6d316e8767 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1037,8 +1037,8 @@ static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent, * Called from TCG-generated code, which is under an RCU read-side * critical section. */ -static void tlb_set_page_full(CPUState *cpu, int mmu_idx, - vaddr addr, CPUTLBEntryFull *full) +static CPUTLBEntryTree *tlb_set_page_full(CPUState *cpu, int mmu_idx, + vaddr addr, CPUTLBEntryFull *full) { CPUTLB *tlb = &cpu->neg.tlb; CPUTLBDesc *desc = &tlb->d[mmu_idx]; @@ -1187,6 +1187,8 @@ static void tlb_set_page_full(CPUState *cpu, int mmu_idx, copy_tlb_helper_locked(te, &node->copy); desc->n_used_entries++; qemu_spin_unlock(&tlb->c.lock); + + return node; } static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, @@ -1266,18 +1268,14 @@ static bool tlb_lookup(CPUState *cpu, TLBLookupOutput *o, tcg_debug_assert(probe); return false; } - tlb_set_page_full(cpu, i->mmu_idx, addr, &o->full); + node = tlb_set_page_full(cpu, i->mmu_idx, addr, &o->full); o->did_tlb_fill = true; if (access_type == MMU_INST_FETCH) { - node = tlbtree_lookup_addr(desc, addr); - tcg_debug_assert(node); goto found_code; } - entry = tlbfast_entry(fast, addr); - cmp = tlb_read_idx(entry, access_type); - node = entry->tree; + cmp = tlb_read_idx(&node->copy, access_type); /* * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, * to force the next access through tlb_fill_align. We've just