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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9bab70sm1417926b3a.152.2024.11.14.08.05.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:05:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 50/54] target/xtensa: Convert to TCGCPUOps.tlb_fill_align Date: Thu, 14 Nov 2024 08:01:26 -0800 Message-ID: <20241114160131.48616-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/xtensa/cpu.h | 8 +++++--- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 28 ++++++++++++++++++++-------- 3 files changed, 26 insertions(+), 12 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 77e48eef19..68c3d90d41 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -31,6 +31,7 @@ #include "cpu-qom.h" #include "qemu/cpu-float.h" #include "exec/cpu-defs.h" +#include "exec/memop.h" #include "hw/clock.h" #include "xtensa-isa.h" @@ -580,9 +581,10 @@ struct XtensaCPUClass { }; #ifndef CONFIG_USER_ONLY -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool xtensa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039abae..3e4ec97e0e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,7 +232,7 @@ static const TCGCPUOps xtensa_tcg_ops = { .restore_state_to_opc = xtensa_restore_state_to_opc, #ifndef CONFIG_USER_ONLY - .tlb_fill = xtensa_cpu_tlb_fill, + .tlb_fill_align = xtensa_cpu_tlb_fill_align, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .cpu_exec_halt = xtensa_cpu_has_work, .do_interrupt = xtensa_cpu_do_interrupt, diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index ca214b948a..69b0e661c8 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -261,15 +261,26 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, addr); } -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool xtensa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUXtensaState *env = cpu_env(cs); uint32_t paddr; uint32_t page_size; unsigned access; - int ret = xtensa_get_physical_addr(env, true, address, access_type, + int ret; + + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + if (probe) { + return false; + } + xtensa_cpu_do_unaligned_access(cs, address, access_type, + mmu_idx, retaddr); + } + + ret = xtensa_get_physical_addr(env, true, address, access_type, mmu_idx, &paddr, &page_size, &access); qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx @@ -277,10 +288,11 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, __func__, address, access_type, mmu_idx, paddr, ret); if (ret == 0) { - tlb_set_page(cs, - address & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); + memset(out, 0, sizeof(*out)); + out->phys_addr = paddr; + out->prot = access; + out->lg_page_size = ctz32(page_size); + out->attrs = MEMTXATTRS_UNSPECIFIED; return true; } else if (probe) { return false;