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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.02.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:02:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 35/54] target/avr: Convert to TCGCPUOps.tlb_fill_align Date: Thu, 14 Nov 2024 08:01:11 -0800 Message-ID: <20241114160131.48616-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 7 ++++--- target/avr/cpu.c | 2 +- target/avr/helper.c | 19 ++++++++++++------- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4725535102..cdd3bcd418 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memop.h" #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -238,9 +239,9 @@ static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg) env->sregI = (sreg >> 7) & 0x01; } -bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool avr_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); #include "exec/cpu-all.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3132842d56..a7fe869396 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -211,7 +211,7 @@ static const TCGCPUOps avr_tcg_ops = { .restore_state_to_opc = avr_restore_state_to_opc, .cpu_exec_interrupt = avr_cpu_exec_interrupt, .cpu_exec_halt = avr_cpu_has_work, - .tlb_fill = avr_cpu_tlb_fill, + .tlb_fill_align = avr_cpu_tlb_fill_align, .do_interrupt = avr_cpu_do_interrupt, }; diff --git a/target/avr/helper.c b/target/avr/helper.c index 345708a1b3..a18f11aa9f 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -104,11 +104,11 @@ hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return addr; /* I assume 1:1 address correspondence */ } -bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool avr_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra) { - int prot, page_size = TARGET_PAGE_SIZE; + int prot, lg_page_size = TARGET_PAGE_BITS; uint32_t paddr; address &= TARGET_PAGE_MASK; @@ -141,15 +141,20 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * to force tlb_fill to be called for the next access. */ if (probe) { - page_size = 1; + lg_page_size = 0; } else { cpu_env(cs)->fullacc = 1; - cpu_loop_exit_restore(cs, retaddr); + cpu_loop_exit_restore(cs, ra); } } } - tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); + memset(out, 0, sizeof(*out)); + out->phys_addr = paddr; + out->prot = prot; + out->attrs = MEMTXATTRS_UNSPECIFIED; + out->lg_page_size = lg_page_size; + return true; }