| Message ID | 20241112181044.92193-18-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls | expand |
On Tue, Nov 12, 2024 at 07:10:41PM +0100, Philippe Mathieu-Daudé wrote: > Add TX_GIE to the TX registers MMIO region. > > Before TX_GIE1 was accessed as RAM, with no effect. > Now it is accessed as MMIO, also without any effect. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> > --- > hw/net/xilinx_ethlite.c | 17 +++++++---------- > 1 file changed, 7 insertions(+), 10 deletions(-) > > diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c > index 159b2b0c64..f7a5b1620a 100644 > --- a/hw/net/xilinx_ethlite.c > +++ b/hw/net/xilinx_ethlite.c > @@ -39,7 +39,6 @@ > > #define R_TX_BUF0 0 > #define A_TX_BASE0 0x07f4 > -#define R_TX_GIE0 (0x07f8 / 4) > #define R_TX_CTRL0 (0x07fc / 4) > #define R_TX_BUF1 (0x0800 / 4) > #define A_TX_BASE1 0x0ff4 > @@ -55,6 +54,7 @@ > > enum { > TX_LEN = 0, > + TX_GIE = 1, > TX_MAX > }; > > @@ -140,6 +140,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) > case TX_LEN: > r = s->port[port_index].reg.tx_len; > break; > + case TX_GIE: > + r = s->port[port_index].reg.tx_gie; > + break; > default: > g_assert_not_reached(); > } > @@ -156,6 +159,9 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, > case TX_LEN: > s->port[port_index].reg.tx_len = value; > break; > + case TX_GIE: > + s->port[port_index].reg.tx_gie = value; > + break; > default: > g_assert_not_reached(); > } > @@ -233,10 +239,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) > > switch (addr) > { > - case R_TX_GIE0: > - r = s->port[port_index].reg.tx_gie; > - break; > - > case R_TX_CTRL1: > case R_TX_CTRL0: > r = s->port[port_index].reg.tx_ctrl; > @@ -281,11 +283,6 @@ eth_write(void *opaque, hwaddr addr, > s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); > break; > > - /* Keep these native. */ > - case R_TX_GIE0: > - s->port[port_index].reg.tx_gie = value; > - break; > - > default: > s->regs[addr] = tswap32(value); > break; > -- > 2.45.2 >
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 159b2b0c64..f7a5b1620a 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -39,7 +39,6 @@ #define R_TX_BUF0 0 #define A_TX_BASE0 0x07f4 -#define R_TX_GIE0 (0x07f8 / 4) #define R_TX_CTRL0 (0x07fc / 4) #define R_TX_BUF1 (0x0800 / 4) #define A_TX_BASE1 0x0ff4 @@ -55,6 +54,7 @@ enum { TX_LEN = 0, + TX_GIE = 1, TX_MAX }; @@ -140,6 +140,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) case TX_LEN: r = s->port[port_index].reg.tx_len; break; + case TX_GIE: + r = s->port[port_index].reg.tx_gie; + break; default: g_assert_not_reached(); } @@ -156,6 +159,9 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, case TX_LEN: s->port[port_index].reg.tx_len = value; break; + case TX_GIE: + s->port[port_index].reg.tx_gie = value; + break; default: g_assert_not_reached(); } @@ -233,10 +239,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) switch (addr) { - case R_TX_GIE0: - r = s->port[port_index].reg.tx_gie; - break; - case R_TX_CTRL1: case R_TX_CTRL0: r = s->port[port_index].reg.tx_ctrl; @@ -281,11 +283,6 @@ eth_write(void *opaque, hwaddr addr, s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); break; - /* Keep these native. */ - case R_TX_GIE0: - s->port[port_index].reg.tx_gie = value; - break; - default: s->regs[addr] = tswap32(value); break;
Add TX_GIE to the TX registers MMIO region. Before TX_GIE1 was accessed as RAM, with no effect. Now it is accessed as MMIO, also without any effect. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/net/xilinx_ethlite.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-)