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[176.184.27.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed987d33sm16160546f8f.43.2024.11.12.09.20.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 09:20:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aurelien Jarno Subject: [PATCH v2 4/6] target/mips: Decode LSA shift amount using decodetree function Date: Tue, 12 Nov 2024 18:20:20 +0100 Message-ID: <20241112172022.88348-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112172022.88348-1-philmd@linaro.org> References: <20241112172022.88348-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 3 ++- target/mips/tcg/rel6.decode | 4 +++- target/mips/tcg/msa_translate.c | 4 ++-- target/mips/tcg/rel6_translate.c | 9 +++++++-- 4 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 4410e2a02e..798e8c401a 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -21,6 +21,7 @@ &msa_elm_df df wd ws n &msa_elm wd ws +%lsa_sa 6:2 !function=plus_1 %elm_df 16:6 !function=elm_df %elm_n 16:6 !function=elm_n %bit_df 16:7 !function=bit_df @@ -29,7 +30,7 @@ %3r_df_h 21:1 !function=plus_1 %3r_df_w 21:1 !function=plus_2 -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r +@lsa ...... rs:5 rt:5 rd:5 ... .. ...... &r sa=%lsa_sa @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:s16 &msa_bz diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode index d6989cf56e..a9031171b5 100644 --- a/target/mips/tcg/rel6.decode +++ b/target/mips/tcg/rel6.decode @@ -16,7 +16,9 @@ &r rs rt rd sa -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r +%lsa_sa 6:2 !function=plus_1 + +@lsa ...... rs:5 rt:5 rd:5 ... .. ...... &r sa=%lsa_sa LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 82b149922f..75cf80a20e 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -780,7 +780,7 @@ TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); static bool trans_LSA(DisasContext *ctx, arg_r *a) { - return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } static bool trans_DLSA(DisasContext *ctx, arg_r *a) @@ -788,5 +788,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a) if (TARGET_LONG_BITS != 64) { return false; } - return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); + return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); } diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index 363bc86491..2522ecae2b 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -11,6 +11,11 @@ #include "qemu/osdep.h" #include "translate.h" +static inline int plus_1(DisasContext *ctx, int x) +{ + return x + 1; +} + /* Include the auto-generated decoders. */ #include "decode-rel6.c.inc" @@ -23,7 +28,7 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) static bool trans_LSA(DisasContext *ctx, arg_r *a) { - return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } static bool trans_DLSA(DisasContext *ctx, arg_r *a) @@ -31,5 +36,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a) if (TARGET_LONG_BITS != 64) { return false; } - return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); + return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); }