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[176.184.43.163]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432b053069fsm192795565e9.4.2024.11.11.14.29.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 11 Nov 2024 14:29:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pavel Dovgalyuk Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 1/3] target/mips: Extract gen_base_index_addr() helper Date: Mon, 11 Nov 2024 23:29:34 +0100 Message-ID: <20241111222936.59869-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241111222936.59869-1-philmd@linaro.org> References: <20241111222936.59869-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Factor out gen_base_index_addr() which is used twice but we'll use it more. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 1 + target/mips/tcg/translate.c | 27 +++++++++++++-------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 1bf153d183..ed69ba15e5 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -153,6 +153,7 @@ void check_cp1_registers(DisasContext *ctx, int regs); void check_cop1x(DisasContext *ctx); void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); +void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index); void gen_move_low32(TCGv ret, TCGv_i64 arg); void gen_move_high32(TCGv ret, TCGv_i64 arg); void gen_load_gpr(TCGv t, int reg); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index de7045874d..7152f5418e 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1956,6 +1956,17 @@ void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset) } } +void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index) +{ + if (base == 0) { + gen_load_gpr(addr, index); + } else if (index == 0) { + gen_load_gpr(addr, base); + } else { + gen_op_addr_add(ctx, addr, cpu_gpr[base], cpu_gpr[index]); + } +} + static target_ulong pc_relative_pc(DisasContext *ctx) { target_ulong pc = ctx->base.pc_next; @@ -10545,13 +10556,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv t0 = tcg_temp_new(); - if (base == 0) { - gen_load_gpr(t0, index); - } else if (index == 0) { - gen_load_gpr(t0, base); - } else { - gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); - } + gen_base_index_addr(ctx, t0, base, index); /* * Don't do NOP if destination is zero: we must perform the actual * memory access. @@ -11333,13 +11338,7 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc, } t0 = tcg_temp_new(); - if (base == 0) { - gen_load_gpr(t0, offset); - } else if (offset == 0) { - gen_load_gpr(t0, base); - } else { - gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); - } + gen_base_index_addr(ctx, t0, base, offset); switch (opc) { case OPC_LBUX: