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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd8e848csm222180125e9.3.2024.11.05.05.05.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:05:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 06/19] hw/microblaze: Fix MemoryRegionOps coding style Date: Tue, 5 Nov 2024 14:04:18 +0100 Message-ID: <20241105130431.22564-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fix few MemoryRegionOps style before adding new fields in the following commits. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/xilinx_uartlite.c | 4 ++-- hw/intc/xilinx_intc.c | 4 ++-- hw/net/xilinx_ethlite.c | 4 ++-- hw/timer/xilinx_timer.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index f325084f8b9..a69ad769cc4 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -172,8 +172,8 @@ static const MemoryRegionOps uart_ops = { .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 1, - .max_access_size = 4 - } + .max_access_size = 4, + }, }; static Property xilinx_uartlite_properties[] = { diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 6e5012e66eb..2b8246f6206 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -146,8 +146,8 @@ static const MemoryRegionOps pic_ops = { .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, - .max_access_size = 4 - } + .max_access_size = 4, + }, }; static void irq_handler(void *opaque, int irq, int level) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index bd812908085..11eb53c4d60 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -172,8 +172,8 @@ static const MemoryRegionOps eth_ops = { .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, - .max_access_size = 4 - } + .max_access_size = 4, + }, }; static bool eth_can_rx(NetClientState *nc) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 32a9df69e0b..0822345779c 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -195,8 +195,8 @@ static const MemoryRegionOps timer_ops = { .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, - .max_access_size = 4 - } + .max_access_size = 4, + }, }; static void timer_hit(void *opaque)