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[92.88.170.46]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2947fbesm593809866b.128.2024.09.30.15.12.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 15:12:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Peter Maydell , Thomas Huth , Hao Wu , Laurent Vivier , Joel Stanley , qemu-arm@nongnu.org, Andrew Jeffery , Steven Lee , Tyrone Ting , "Edgar E. Iglesias" , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Jamin Lin , Troy Lee , Anton Johansson Subject: [PATCH 1/3] target/arm: Expose arm_cpu_code_is_big_endian() prototype in 'cpu.h' Date: Tue, 1 Oct 2024 00:12:02 +0200 Message-ID: <20240930221205.59101-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930221205.59101-1-philmd@linaro.org> References: <20240930221205.59101-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expose arm_cpu_code_is_big_endian() so it can be used by hw/ code. Use it in few places where it was open coded. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 7 +++++++ linux-user/aarch64/cpu_loop.c | 4 ++-- linux-user/arm/cpu_loop.c | 4 ++-- target/arm/cpu.c | 6 ++---- 4 files changed, 13 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f065756c5c..da8f2b2ec8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3057,6 +3057,13 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) } } +static inline bool bswap_code(bool sctlr_b); + +static inline bool arm_cpu_code_is_big_endian(CPUARMState *env) +{ + return bswap_code(arm_sctlr_b(env)); +} + #include "exec/cpu-all.h" /* diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 71cdc8be50..68ff3c14f8 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -29,7 +29,7 @@ #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ + if (!__r && arm_cpu_code_is_big_endian(env)) { \ (x) = bswap32(x); \ } \ __r; \ @@ -37,7 +37,7 @@ #define get_user_code_u16(x, gaddr, env) \ ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ + if (!__r && arm_cpu_code_is_big_endian(env)) { \ (x) = bswap16(x); \ } \ __r; \ diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ec665862d9..0cc056be31 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -29,7 +29,7 @@ #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ + if (!__r && arm_cpu_code_is_big_endian(env)) { \ (x) = bswap32(x); \ } \ __r; \ @@ -37,7 +37,7 @@ #define get_user_code_u16(x, gaddr, env) \ ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ + if (!__r && arm_cpu_code_is_big_endian(env)) { \ (x) = bswap16(x); \ } \ __r; \ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c2391..f3198ee2f2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1167,7 +1167,6 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) { ARMCPU *ac = ARM_CPU(cpu); CPUARMState *env = &ac->env; - bool sctlr_b; if (is_a64(env)) { info->cap_arch = CS_ARCH_ARM64; @@ -1194,8 +1193,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) info->cap_mode = cap_mode; } - sctlr_b = arm_sctlr_b(env); - if (bswap_code(sctlr_b)) { + if (arm_cpu_code_is_big_endian(env)) { #if TARGET_BIG_ENDIAN info->endian = BFD_ENDIAN_LITTLE; #else @@ -1204,7 +1202,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) } info->flags &= ~INSN_ARM_BE32; #ifndef CONFIG_USER_ONLY - if (sctlr_b) { + if (arm_sctlr_b(env)) { info->flags |= INSN_ARM_BE32; } #endif