From patchwork Sun Sep 22 12:00:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 830121 Delivered-To: patch@linaro.org Received: by 2002:adf:ebcc:0:b0:367:895a:4699 with SMTP id v12csp1553532wrn; Sun, 22 Sep 2024 05:03:53 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUJNLgkuHtoKHAGJd2nxcqlyt8z9z8ArDjzcEYTxhUycoAx9lwMlq2Pz/z6f5QUr+In2bASiA==@linaro.org X-Google-Smtp-Source: AGHT+IE4bL4vOjepgDTs5ajxgEkpelGh9a9Pv/0zbeYqk/yZeIPGU/3VIZO3+Q5/jhD6Ll4O55mN X-Received: by 2002:a05:620a:450a:b0:7a6:5a80:7ee7 with SMTP id af79cd13be357-7acb8209cd4mr1594729085a.46.1727006632973; Sun, 22 Sep 2024 05:03:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727006632; cv=none; d=google.com; s=arc-20240605; b=WWMJqAGIC6Efztx1Cj6s/qI8qQyBqoOzqd3w87RmQO083iXw+8ZDsjmEgO6jW2iOR+ eSAmw2tk+b7/c7Snm96+QZt+PWMxmBZPq8h2iDLZ3YS1jSgvMdyCcIrNvjWGPxhpapvp 8K/gFVhlrK6+CMNISlL7GJ9oyzmzWQZ3h8ORVT8rfbBtHKWGfJlk3UGEmcJZuCQdeD2i zOutWbW01eBEpruhd+Cl6+oXEb1SFuHXsFZNL+thxSpWga92Cm52hsgYkkxcNLMg5HUf kVgFf3NHMAwaUfQJtqqz/eg/1Ct3tk8nzz2xmET9P4Tflf2xHDezgnxUGlG3fPC+Eahx vNlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9crvsERH/myYSJkgKez5YbnhkNv578itQ81kZkhssYk=; fh=UQCixiNfr28ZOrfhmxiGPA65dFhly8CmRsnoYC6xI9k=; b=C3KXUx/+r1/PF+xslEDoI9GFDxCXPXZDJXTFQ6hqnkBun5XC1kHJost9bOFlqNU2dA gYE5wb+XPEqUG43+uS9KKsvU+YpCfh8aQ0UNU6+zcyc8ySJghB+V09i4umirAc2IcR6C JucAvH/7jalb172ftnEQL+ewMFdHtvC2zMZS7bwTiFCOtB9H8RUXSt3zuomsbjBiPvjZ xJdwnUah1tDYczbNzPjqM4ZXueUC+dGxrirxq0WE71G4+bHMbjMBD52DHbXIL4WQdsew k71B0SzncRxRj0YsfTCaz0lP+u8u703B5eIMCzBWK0NMXS2EE+pwxd1npICftndFJxce O+EA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nEj1DJC1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-45b178696e6si81941951cf.76.2024.09.22.05.03.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 22 Sep 2024 05:03:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nEj1DJC1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ssLHv-0002cy-DW; Sun, 22 Sep 2024 08:02:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ssLHL-0000vr-LU for qemu-devel@nongnu.org; Sun, 22 Sep 2024 08:01:33 -0400 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ssLHG-0002NB-IA for qemu-devel@nongnu.org; Sun, 22 Sep 2024 08:01:24 -0400 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a8a789c4fc5so757456966b.0 for ; Sun, 22 Sep 2024 05:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727006479; x=1727611279; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9crvsERH/myYSJkgKez5YbnhkNv578itQ81kZkhssYk=; b=nEj1DJC1INVRdgnKT1men9mfrWfVQqpfhmbehp4ls69BkVzK60SYN40hpt+KV1WkP/ ilnGluhNSJtiDbBTx+99GsxL0IuWf7NMRn/gG9f4vRWXBWAvp04oZWCABJBMzLErW7DD Qv3IqK6yoss1h+95olB4Zjo8GItNqJd2EXnkfpigXYR0gAo/X2Rzn2PkJ3U5QtkGaLJq 5BpPQuTnT2e8HP8efnrU4+C30uBBOer8t+uzNWxTaG0P58+NckuyUocu6KfbosI1k0d1 G5Nr4MeNYIEcttcqPbURlqxHTBz8SYFEpMi0THY9RnIM1toNUHV5UYoye43czqtDqsc2 Iyzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727006479; x=1727611279; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9crvsERH/myYSJkgKez5YbnhkNv578itQ81kZkhssYk=; b=LKCy8nose+sXM+FEux8vCk0wHpSlEgumWFeR/I+AZg/TOKXqaiCLl9bTCOdoCeCNDX YzRi9JWqH/SYhibgIKmLaGw/jwxTM3XmzoXE9lhIP9154RyM2Es1RHxLWcMfKOBQtzXN +jEYlRMbDtplk+zMAtFgKnTtXGZGiiirX/nBA5XEXplHi73X4adDNh/Eklks9F67BptN UWbrVQq5tmWEbGFPNrjBFAevqhlW4P3QQ1T86NMpHaybwfNVVpjMiJwkJ+oB2MATC4FP ntWhuvFbH/mFdvCms2pW2y9DEmp+VgmBWYBjaRvcmJfJv45ThgJo1nk6FP2mPpDr3j/t 7UHw== X-Gm-Message-State: AOJu0Yz9AH7sZoUFoIJAoG29p2eVSOwi4L6GD5NsYfkt/5+SjpNop6RC jLRL3JKsjuNpReY5x3vmKs0t9IsPyIGqnLkHXhI3BVqcDSG09PwNi2wdjr8svnW91xzrgdIWkGj e3bA= X-Received: by 2002:a17:907:7288:b0:a8d:4c83:d85d with SMTP id a640c23a62f3a-a90c1c77fc6mr1486526666b.12.1727006478541; Sun, 22 Sep 2024 05:01:18 -0700 (PDT) Received: from stoup.. (90-181-218-29.rco.o2.cz. [90.181.218.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a90612df525sm1067909966b.159.2024.09.22.05.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Sep 2024 05:01:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PULL 08/31] tcg/ppc: Do not expand cmp_vec early Date: Sun, 22 Sep 2024 14:00:49 +0200 Message-ID: <20240922120112.5067-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240922120112.5067-1-richard.henderson@linaro.org> References: <20240922120112.5067-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move expansion to opcode generation. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 169 +++++++++++++++++++++------------------ 1 file changed, 90 insertions(+), 79 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3553a47ba9..497e130581 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3567,12 +3567,13 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: return vece <= MO_32; - case INDEX_op_cmp_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: case INDEX_op_rotli_vec: return vece <= MO_32 || have_isa_2_07 ? -1 : 0; + case INDEX_op_cmp_vec: + return vece <= MO_32 || have_isa_2_07 ? 1 : 0; case INDEX_op_neg_vec: return vece >= MO_32 && have_isa_3_00; case INDEX_op_mul_vec: @@ -3713,6 +3714,90 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, return true; } +static void tcg_out_not_vec(TCGContext *s, TCGReg a0, TCGReg a1) +{ + tcg_out32(s, VNOR | VRT(a0) | VRA(a1) | VRB(a1)); +} + +static bool tcg_out_cmp_vec_noinv(TCGContext *s, unsigned vece, TCGReg a0, + TCGReg a1, TCGReg a2, TCGCond cond) +{ + static const uint32_t + eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, + ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, + gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, + gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }; + uint32_t insn; + + bool need_swap = false, need_inv = false; + + tcg_debug_assert(vece <= MO_32 || have_isa_2_07); + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + case TCG_COND_GTU: + break; + case TCG_COND_NE: + if (have_isa_3_00 && vece <= MO_32) { + break; + } + /* fall through */ + case TCG_COND_LE: + case TCG_COND_LEU: + need_inv = true; + break; + case TCG_COND_LT: + case TCG_COND_LTU: + need_swap = true; + break; + case TCG_COND_GE: + case TCG_COND_GEU: + need_swap = need_inv = true; + break; + default: + g_assert_not_reached(); + } + + if (need_inv) { + cond = tcg_invert_cond(cond); + } + if (need_swap) { + TCGReg swap = a1; + a1 = a2; + a2 = swap; + cond = tcg_swap_cond(cond); + } + + switch (cond) { + case TCG_COND_EQ: + insn = eq_op[vece]; + break; + case TCG_COND_NE: + insn = ne_op[vece]; + break; + case TCG_COND_GT: + insn = gts_op[vece]; + break; + case TCG_COND_GTU: + insn = gtu_op[vece]; + break; + default: + g_assert_not_reached(); + } + tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); + + return need_inv; +} + +static void tcg_out_cmp_vec(TCGContext *s, unsigned vece, TCGReg a0, + TCGReg a1, TCGReg a2, TCGCond cond) +{ + if (tcg_out_cmp_vec_noinv(s, vece, a0, a1, a2, cond)) { + tcg_out_not_vec(s, a0, a0); + } +} + static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg args[TCG_MAX_OP_ARGS], @@ -3723,10 +3808,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, mul_op[4] = { 0, 0, VMULUWM, VMULLD }, neg_op[4] = { 0, 0, VNEGW, VNEGD }, - eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, - ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, - gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, - gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, @@ -3820,9 +3901,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, insn = VANDC; break; case INDEX_op_not_vec: - insn = VNOR; - a2 = a1; - break; + tcg_out_not_vec(s, a0, a1); + return; case INDEX_op_orc_vec: insn = VORC; break; @@ -3837,23 +3917,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_cmp_vec: - switch (args[3]) { - case TCG_COND_EQ: - insn = eq_op[vece]; - break; - case TCG_COND_NE: - insn = ne_op[vece]; - break; - case TCG_COND_GT: - insn = gts_op[vece]; - break; - case TCG_COND_GTU: - insn = gtu_op[vece]; - break; - default: - g_assert_not_reached(); - } - break; + tcg_out_cmp_vec(s, vece, a0, a1, a2, args[3]); + return; case INDEX_op_bitsel_vec: tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); @@ -3921,56 +3986,6 @@ static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, tcgv_vec_arg(v1), tcgv_vec_arg(t1)); } -static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec v2, TCGCond cond) -{ - bool need_swap = false, need_inv = false; - - tcg_debug_assert(vece <= MO_32 || have_isa_2_07); - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_GT: - case TCG_COND_GTU: - break; - case TCG_COND_NE: - if (have_isa_3_00 && vece <= MO_32) { - break; - } - /* fall through */ - case TCG_COND_LE: - case TCG_COND_LEU: - need_inv = true; - break; - case TCG_COND_LT: - case TCG_COND_LTU: - need_swap = true; - break; - case TCG_COND_GE: - case TCG_COND_GEU: - need_swap = need_inv = true; - break; - default: - g_assert_not_reached(); - } - - if (need_inv) { - cond = tcg_invert_cond(cond); - } - if (need_swap) { - TCGv_vec t1; - t1 = v1, v1 = v2, v2 = t1; - cond = tcg_swap_cond(cond); - } - - vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); - - if (need_inv) { - tcg_gen_not_vec(vece, v0, v0); - } -} - static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) { @@ -4045,10 +4060,6 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotli_vec: expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); break; - case INDEX_op_cmp_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); - break; case INDEX_op_mul_vec: v2 = temp_tcgv_vec(arg_temp(a2)); expand_vec_mul(type, vece, v0, v1, v2);