From patchwork Mon Sep 9 17:28:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 826634 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp2130948wrb; Mon, 9 Sep 2024 10:31:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVSD91lFlaMqZhvTA0g+F6hxrJbh3USRGL2miCZUehq7gj6SVAiJsF9YABbZUPxvj/GybzNAg==@linaro.org X-Google-Smtp-Source: AGHT+IFo9fm+Keq1frukYE5+ofoZ2xZc5nf4KGX3FPeYtrEJ8mJ5EgObilKUFkapBYJFvFVUFWAL X-Received: by 2002:a05:6102:d93:b0:493:c8b9:67d3 with SMTP id ada2fe7eead31-49bde267e6cmr12577783137.20.1725903092582; Mon, 09 Sep 2024 10:31:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725903092; cv=none; d=google.com; s=arc-20240605; b=JQ7k8Z7DUdJ8mj8v1UKyWCQsHDCf+Ax9Te1fVXs28TfPK2Rwprv6HrWTpR0V9md2hc E0amAp3/881Ol3afEK/cOblDZ4KpJlfuO7pIEXvRFP1GupKD8+z2FKn211dnR5KdfPSX f9nvXao70/cjIeG7aCYsE4xGWZYKNGOLViviy6+CXMNTUVqm6cBKfhK/h5JuZOZp+nAT EfpKU2KlbErY4HFo8wccJS1O9DCCI83x9I6iJ2UliLga/Gx6IPBZ2guWiJrIgMxejsVI VpBitX3GwDoINzchlXAPs46fqNG5ccBS3dFkmrzmFzCWjV1MYF92RDkYMepCxYydTHNT JaLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9Q+lRBnZtbiSxP2XFIjmwjdFQ0N8KmnUCAkdueIhYHQ=; fh=4bMsMJJHDmTQNFavmZaD/iTPOPK/LdH9YFdHoY+StpE=; b=eaJ4lNKa2iwCnIkgsFOJVrcBUyo7CPJGXA1ORkVq4tEgqLcvArDvS3senFbZAS3sJA U/0LpEhZhN6r+I8/BDbbSUBFottINg29fSgGCoPvAUoZTENIdpq4wapYDSNZsMIWDPHp rq7YH6zis332shyRaBLrTJs+7za98X2q3QYCvNaR53Jzfy+H5RY3Dub+faQnT8fdPkh3 Ud/nsfYek5FAJ7qhRCx1slMH6A/c7+18LNKgv7jIlFwoLHv1LfNtknEVdELb1Xx3Qnm9 QACE7LSh2lZmKv4kqQFE9w6SYHEFZeuB9ojChNUufRrYk/nbfVJOFaCSAO2Fnc6NI5mB 5ybw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HSyGpaUu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-49bf0aa34cdsi998426137.648.2024.09.09.10.31.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Sep 2024 10:31:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HSyGpaUu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sniC4-0005N2-Ln; Mon, 09 Sep 2024 13:28:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sniBt-0004YT-ET for qemu-devel@nongnu.org; Mon, 09 Sep 2024 13:28:41 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sniBr-00062R-1b for qemu-devel@nongnu.org; Mon, 09 Sep 2024 13:28:41 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-20551eeba95so40961145ad.2 for ; Mon, 09 Sep 2024 10:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1725902917; x=1726507717; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Q+lRBnZtbiSxP2XFIjmwjdFQ0N8KmnUCAkdueIhYHQ=; b=HSyGpaUuQ/orhP/U4RXU3WfOeg7r2cfq71wza2KSCW9c0IKtje6e2c2A5LBCvotBz2 wNGdsxVMfA+C9oRCeSnkMWzYRYyck1oaoHAoGq4gevUvpCBg9Bd3uvYqFixYPUt8gAYh 63A8yeTbwc9gnbveynZD5wOTm74T6phQy4nBZdS9qG6I0MYMRKM6i61zg2x95/f0SxII UNzZmwhqzxhDfYBEKEh0bFH9pEMhFMT4S3KP78Mk8rufldBGsYkFoqSh/OTXodGGJBW3 8O7lm9OfHSfOQWaTJjUcvJnj0YbZHoeBFbnjyueajR5X35yRUwukapOxCWHHUbNynak5 VpUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725902917; x=1726507717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Q+lRBnZtbiSxP2XFIjmwjdFQ0N8KmnUCAkdueIhYHQ=; b=RuD1vzXkHhQeMD/iBnT9buSXfsSqRh31Vd44WZLWr2GEHMB0bQIfLoL/DolW6ntcxd cldXOtxkgTd1et/wR/AAIV0CzDgdC7jnj1zzEJRcmHTdOZi9dow7tszKvxI8TPloPEgZ K8mKZu9DCtlM8LPa7SXL1+5hKUnUiNliZSkWtfKLDyBe3qsUVG1NAY42UbUdkULVDLT1 zH84rZVH64fHLy157YGhXk0DJCGkEAKpE7N3BBAkEJvZWLsGvC9l2k/z9oU5A29/hcc1 TTAbmyBj9FeTn2BFXM3A6ygPdp4BoKquQxGSS21z2NnVtFlMQqtQu64TUZRKSXvBmIZV vMmg== X-Gm-Message-State: AOJu0YzRtuEYWmbFjTYBTT4rpIOg5moj+m0orIwnZe6fPm/UHHk1aJVm /TndJpjDCGdpbfEWYuLuR/U3KjNsF46yntPmsfYwyNkAQGWNB39f6WY0mnPf2WOJZgqiwIpGNhy w X-Received: by 2002:a17:902:e80e:b0:206:d6ac:854f with SMTP id d9443c01a7336-206f049d45amr97386985ad.3.1725902917127; Mon, 09 Sep 2024 10:28:37 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20710e11e02sm36539875ad.14.2024.09.09.10.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 10:28:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, daniel@0x0f.com Subject: [PATCH v3 13/26] target/m68k: Split gen_ea_mode for load/store Date: Mon, 9 Sep 2024 10:28:10 -0700 Message-ID: <20240909172823.649837-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240909172823.649837-1-richard.henderson@linaro.org> References: <20240909172823.649837-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with gen_load_mode and gen_store_mode. Return bool for success from gen_store_mode, which makes store_dummy unused. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 155 ++++++++++++++++++++-------------------- 1 file changed, 76 insertions(+), 79 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c6b901ff83..2c0852ac3a 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -59,8 +59,6 @@ static TCGv_i64 cpu_macc[4]; static TCGv NULL_QREG; #define IS_NULL_QREG(t) (t == NULL_QREG) -/* Used to distinguish stores from bad addressing modes. */ -static TCGv store_dummy; void m68k_tcg_init(void) { @@ -104,7 +102,6 @@ void m68k_tcg_init(void) } NULL_QREG = tcg_global_mem_new(tcg_env, -4, "NULL"); - store_dummy = tcg_global_mem_new(tcg_env, -8, "NULL"); } /* internal defines */ @@ -338,21 +335,6 @@ typedef enum { EA_LOADS } ea_what; -/* - * Generate an unsigned load if VAL is 0 a signed load if val is -1, - * otherwise generate a store. - */ -static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, - ea_what what, int index) -{ - if (what == EA_STORE) { - gen_store(s, opsize, addr, val, index); - return store_dummy; - } else { - return gen_load(s, opsize, addr, what == EA_LOADS, index); - } -} - /* Read a 16-bit immediate constant */ static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) { @@ -794,9 +776,9 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, * a write otherwise it is a read (0 == sign extend, -1 == zero extend). * ADDRP is non-null for readwrite operands. */ -static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, - int opsize, TCGv val, TCGv *addrp, ea_what what, - int index) +static TCGv gen_load_mode(CPUM68KState *env, DisasContext *s, + int mode, int reg0, int opsize, TCGv *addrp, + int sign, int index) { TCGv reg, ret, addr = NULL; int32_t offset; @@ -804,40 +786,28 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, switch (mode) { case 0: /* Data register direct. */ reg = cpu_dregs[reg0]; - if (what == EA_STORE) { - gen_partset_reg(opsize, reg, val); - ret = store_dummy; - } else { - ret = gen_extend(s, reg, opsize, what == EA_LOADS); - } + ret = gen_extend(s, reg, opsize, sign); break; case 1: /* Address register direct. */ reg = get_areg(s, reg0); - if (what == EA_STORE) { - tcg_gen_mov_i32(reg, val); - ret = store_dummy; - } else { - ret = gen_extend(s, reg, opsize, what == EA_LOADS); - } + ret = gen_extend(s, reg, opsize, sign); break; case 7: /* Other */ - if (reg0 == 4 && what != EA_STORE) { + if (reg0 == 4) { /* Immediate: sign extend values for consistency. */ switch (opsize) { case OS_BYTE: - if (what == EA_LOADS) { - offset = (int8_t)read_im8(env, s); - } else { - offset = read_im8(env, s); + offset = read_im8(env, s); + if (sign) { + offset = (int8_t)offset; } break; case OS_WORD: - if (what == EA_LOADS) { - offset = (int16_t)read_im16(env, s); - } else { - offset = read_im16(env, s); + offset = read_im16(env, s); + if (sign) { + offset = (int16_t)offset; } break; case OS_LONG: @@ -856,17 +826,13 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, case 4: /* Indirect predecrememnt. */ case 5: /* Indirect displacement. */ case 6: /* Indirect index + displacement. */ - if (what == EA_STORE && addrp && *addrp) { - addr = *addrp; - } else { - addr = gen_lea_mode(env, s, mode, reg0, opsize); - if (IS_NULL_QREG(addr)) { - ret = addr; - addr = NULL; - break; - } + addr = gen_lea_mode(env, s, mode, reg0, opsize); + if (IS_NULL_QREG(addr)) { + ret = addr; + addr = NULL; + break; } - ret = gen_ldst(s, opsize, addr, val, what, index); + ret = gen_load(s, opsize, addr, sign, index); break; default: @@ -879,6 +845,43 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, return ret; } +static bool gen_store_mode(CPUM68KState *env, DisasContext *s, + int mode, int reg0, int opsize, + TCGv val, TCGv addr, int index) +{ + TCGv reg; + + switch (mode) { + case 0: /* Data register direct. */ + reg = cpu_dregs[reg0]; + gen_partset_reg(opsize, reg, val); + return true; + + case 1: /* Address register direct. */ + reg = get_areg(s, reg0); + tcg_gen_mov_i32(reg, val); + return true; + + case 2: /* Indirect register */ + case 3: /* Indirect postincrement. */ + case 4: /* Indirect predecrememnt. */ + case 5: /* Indirect displacement. */ + case 6: /* Indirect index + displacement. */ + case 7: /* Other */ + if (!addr) { + addr = gen_lea_mode(env, s, mode, reg0, opsize); + if (IS_NULL_QREG(addr)) { + return false; + } + } + gen_store(s, opsize, addr, val, index); + return true; + + default: + g_assert_not_reached(); + } +} + static TCGv_ptr gen_fp_ptr(int freg) { TCGv_ptr fp = tcg_temp_new_ptr(); @@ -1321,13 +1324,9 @@ static void gen_exit_tb(DisasContext *s) #define SRC_EA(env, result, opsize, op_sign, addrp) \ do { \ - TCGv *addrp_ = (addrp); \ - if (addrp_) { \ - *addrp_ = NULL; \ - } \ - result = gen_ea_mode(env, s, extract32(insn, 3, 3), \ - REG(insn, 0), opsize, NULL_QREG, addrp_, \ - op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \ + result = gen_load_mode(env, s, extract32(insn, 3, 3), \ + REG(insn, 0), opsize, addrp, \ + op_sign, IS_USER(s)); \ if (IS_NULL_QREG(result)) { \ gen_addr_fault(s); \ return; \ @@ -1336,10 +1335,10 @@ static void gen_exit_tb(DisasContext *s) #define DEST_EA(env, insn, opsize, val, addrp) \ do { \ - TCGv ea_result = gen_ea_mode(env, s, extract32(insn, 3, 3), \ - REG(insn, 0), opsize, val, addrp, \ - EA_STORE, IS_USER(s)); \ - if (IS_NULL_QREG(ea_result)) { \ + TCGv *addrp_ = (addrp); \ + if (!gen_store_mode(env, s, extract32(insn, 3, 3), \ + REG(insn, 0), opsize, val, \ + addrp_ ? *addrp_ : NULL, IS_USER(s))) { \ gen_addr_fault(s); \ return; \ } \ @@ -1701,15 +1700,14 @@ DISAS_INSN(abcd_mem) /* Indirect pre-decrement load (mode 4) */ - src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, - NULL_QREG, NULL, EA_LOADU, IS_USER(s)); - dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, - NULL_QREG, &addr, EA_LOADU, IS_USER(s)); + src = gen_load_mode(env, s, 4, REG(insn, 0), OS_BYTE, + NULL, false, IS_USER(s)); + dest = gen_load_mode(env, s, 4, REG(insn, 9), OS_BYTE, + &addr, false, IS_USER(s)); bcd_add(dest, src); - gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, - EA_STORE, IS_USER(s)); + gen_store_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, addr, IS_USER(s)); bcd_flags(dest); } @@ -1738,15 +1736,14 @@ DISAS_INSN(sbcd_mem) /* Indirect pre-decrement load (mode 4) */ - src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, - NULL_QREG, NULL, EA_LOADU, IS_USER(s)); - dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, - NULL_QREG, &addr, EA_LOADU, IS_USER(s)); + src = gen_load_mode(env, s, 4, REG(insn, 0), OS_BYTE, + NULL, false, IS_USER(s)); + dest = gen_load_mode(env, s, 4, REG(insn, 9), OS_BYTE, + &addr, false, IS_USER(s)); bcd_sub(dest, src); - gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, - EA_STORE, IS_USER(s)); + gen_store_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, addr, IS_USER(s)); bcd_flags(dest); } @@ -3123,11 +3120,11 @@ DISAS_INSN(cmpm) TCGv src, dst; /* Post-increment load (mode 3) from Ay. */ - src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize, - NULL_QREG, NULL, EA_LOADS, IS_USER(s)); + src = gen_load_mode(env, s, 3, REG(insn, 0), opsize, + NULL, true, IS_USER(s)); /* Post-increment load (mode 3) from Ax. */ - dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize, - NULL_QREG, NULL, EA_LOADS, IS_USER(s)); + dst = gen_load_mode(env, s, 3, REG(insn, 9), opsize, + NULL, true, IS_USER(s)); gen_update_cc_cmp(s, dst, src, opsize); }