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Tue, 13 Aug 2024 03:19:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Thomas Petazzoni , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Jiaxun Yang , Waldemar Brodkorb Subject: [PATCH-for-9.1 v2 2/2] target/mips: Use correct MMU index in get_pte() Date: Tue, 13 Aug 2024 12:18:56 +0200 Message-ID: <20240813101856.49469-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240813101856.49469-1-philmd@linaro.org> References: <20240813101856.49469-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte(): page_table_walk_refill() -> get_pte() -> cpu_ld[lq]_code() -> cpu_mmu_index() Since we don't mask anymore the modes in hflags, cpu_mmu_index() can return UM or SM, while we only expect KM or ERL. Fix by propagating ptw_mmu_idx to get_pte(), and use the cpu_ld/st_code_mmu() API with the correct MemOpIdx. Reported-by: Thomas Petazzoni Reported-by: Waldemar Brodkorb Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2470 Fixes: 4e999bf419 ("target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/sysemu/tlb_helper.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index a8caf3ade8..4e64c226a5 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -593,16 +593,21 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, */ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, unsigned entry_bytes, - uint64_t *pte) + uint64_t *pte, unsigned ptw_mmu_idx) { + MemOpIdx oi; + if ((vaddr & (entry_bytes - 1)) != 0) { return false; } + + oi = make_memop_idx(size_memop(entry_bytes) | MO_TE, ptw_mmu_idx); if (entry_bytes == 8) { - *pte = cpu_ldq_code(env, vaddr); + *pte = cpu_ldq_code_mmu(env, vaddr, oi, 0); } else { - *pte = cpu_ldl_code(env, vaddr); + *pte = cpu_ldl_code_mmu(env, vaddr, oi, 0); } + return true; } @@ -643,7 +648,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, /* wrong base address */ return 0; } - if (!get_pte(env, *vaddr, direntry_size, &entry)) { + if (!get_pte(env, *vaddr, direntry_size, &entry, ptw_mmu_idx)) { return 0; } @@ -669,7 +674,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, ptw_mmu_idx) != TLBRET_MATCH) { return 0; } - if (!get_pte(env, vaddr2, leafentry_size, &entry)) { + if (!get_pte(env, vaddr2, leafentry_size, &entry, ptw_mmu_idx)) { return 0; } entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew); @@ -827,7 +832,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, ptw_mmu_idx) != TLBRET_MATCH) { return false; } - if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { + if (!get_pte(env, vaddr, leafentry_size, &dir_entry, ptw_mmu_idx)) { return false; } dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew); @@ -839,7 +844,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, ptw_mmu_idx) != TLBRET_MATCH) { return false; } - if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { + if (!get_pte(env, vaddr, leafentry_size, &dir_entry, ptw_mmu_idx)) { return false; } dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);