From patchwork Thu Jul 18 13:20:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 813171 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp289960wro; Thu, 18 Jul 2024 06:21:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWUdtcoZ8V2oMdSDcZ74CG6/QW9sc2t5Ny+6Bx9NgueFZ1g3yr5Weyy8JZ1CLCU6RHbGTPu8r1Hz3DQkpkALf7/ X-Google-Smtp-Source: AGHT+IEspvrcNyN+nhP8vHx6XxuigOzFqU2KhohnqsJzTNKt30UW4qQ2YhuAyDUBnQPsrWh664se X-Received: by 2002:a05:622a:284:b0:447:f12f:38dd with SMTP id d75a77b69052e-44f96a8bd29mr7648851cf.59.1721308888827; Thu, 18 Jul 2024 06:21:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721308888; cv=none; d=google.com; s=arc-20160816; b=u5jFNC54GXJ7Gy+afwo1/uMOoryyN+/DX2EQdfieZFi0+RJwgiWyhaah3Ak0Ar00QS uJ09FKfX7HMeqOqEL3d2NBC6G1Tcihhk53xM4K6Pp1xHxJNKu67+6+03IXv4FmOwW7Cq pijHlZlKWNuMJs/Vm8/mRPfMoapeaGtNnCAxGn25zCzpL26i0eVq9St/lfiDohEykFDX jaTgXCX48EOVleOGcR568ebCV90mNq4H8CKibbJjfkSLKYRCnN2b260GwFONPo0wyOT2 FNZeSUo4aSs3mwMQm2owPi6/WryzA8vaAXcIoj1k5POkzMnYcfJsNyRripD4H3WjRc9T Paqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v9HD9ARg19Jqe83BWvMljdXei9HAy93M0+v9flXqPJQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Wyl0Znxp/iEJvva7eQh7aqWNIrAFUOa1Lit9wlRMjtKclPBeKbo74gKB7YuYAJO9Ja 41DQNqdBvY4LolDOrLFzZNuckqBJNUcMDXYlnWTFkoyTVNvoMUbKrCpCXtg8ogIYmfZM tK4HaG9fXYPymLzrnfgrhUO/m75XCSYG8cuO3ndf82eCE02QqUECGP+ICBnB1twimC+Y wbqP4mGPBaA1HHQ2eVwRUCsyeuTIXYMuex22L5ZO3QX4FnCbVceCUYhaRR7qK63r8dxF mjVC1rKP7zfCSDu+VU1EHs+1nyLMJ3jkz8JhUlmihLN0TW8X+9T0vA8Footd08L4JlD/ Lz9A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="K3ooLbL/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-44f96a59d65si5664481cf.482.2024.07.18.06.21.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jul 2024 06:21:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="K3ooLbL/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUR4A-000204-V1; Thu, 18 Jul 2024 09:21:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUR3n-00085I-0z for qemu-devel@nongnu.org; Thu, 18 Jul 2024 09:20:40 -0400 Received: from mail-lj1-x229.google.com ([2a00:1450:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sUR3i-0004TC-O4 for qemu-devel@nongnu.org; Thu, 18 Jul 2024 09:20:37 -0400 Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2eeb1ba0468so11465821fa.0 for ; Thu, 18 Jul 2024 06:20:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721308832; x=1721913632; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=v9HD9ARg19Jqe83BWvMljdXei9HAy93M0+v9flXqPJQ=; b=K3ooLbL/4O7X8tEWY9qor/yiDmOB/eRbguIsSJQyVYNViXHvFf39heNva1CRScgUM1 544fm+GZ+oNRDB2Vg/SAg4zsF0nm3IY/84Is79E+1+29j8d6g9rrh7rTh5W8Jv9gm3uA /LGs+lcGAr7PeFV531CuaBIf2iuv6StElHK6kKTQy7ZHgTTAtLPnZVZcNtviNZriJIoJ qKg16x54qQQnZodrbcJjNb4dOvw/5kU35Mu439YRZzNKGQLsGMGX9FJ6ajtgida51A0S MzNgT6/3eCoV3ut9gWFf8RuRTBP/dFLulfnZwFksFLXElJ71FMhgltO166vP0+7Dyj2x iXCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721308832; x=1721913632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v9HD9ARg19Jqe83BWvMljdXei9HAy93M0+v9flXqPJQ=; b=UJ58N8NYEcQnq9m67QGuoM2/citDO8Ky48/3kYVhLKz981996Ieb5d/cZ6I5kKJ6CC 2E4YgHdjao97bvxm3RJsS8cEX6NOags0FSu47iYPNSJtN7l4Hhocv87AChzmEiMvvY46 8UqwNcegMdr0aDJLgZ7U5oK/d5sgdlWHHdw037a4gXFgSABvY7CbSi3+ZhsqfAqhQg/q M7CokF8Y1DFpcW20A/YT5GXl+rMyi37+zH8Sz7B3JAFJuHXAMvZkOka2p27d2o3gL3Vm 7buZuCYc6W0cWf0nhoBDdzwWfhPLfqq+DJqKWd6OcIeHReq6cFgY3va7Mzg3YhD6Sk9U MpAQ== X-Gm-Message-State: AOJu0Yx/33ARx/6W2Mh9vkQ94zNbrQTsRuZ+s88I81n5amn0+dA3KPOx 2sEeMzgifGGbWU0fZaoIhwFDq/xB6A06VnRPXMfFvOIneLA2eMjB3hsxu2+3KL8IxFltrO+v/7x h X-Received: by 2002:a2e:a304:0:b0:2ee:8ce9:3037 with SMTP id 38308e7fff4ca-2ef05d27e3emr17883461fa.37.1721308832561; Thu, 18 Jul 2024 06:20:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2a8e420sm14059315e9.35.2024.07.18.06.20.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 06:20:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/26] hw/arm/smmu: Fix IPA for stage-2 events Date: Thu, 18 Jul 2024 14:20:07 +0100 Message-Id: <20240718132028.697927-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718132028.697927-1-peter.maydell@linaro.org> References: <20240718132028.697927-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Mostafa Saleh For the following events (ARM IHI 0070 F.b - 7.3 Event records): - F_TRANSLATION - F_ACCESS - F_PERMISSION - F_ADDR_SIZE If fault occurs at stage 2, S2 == 1 and: - If translating an IPA for a transaction (whether by input to stage 2-only configuration, or after successful stage 1 translation), CLASS == IN, and IPA is provided. At the moment only CLASS == IN is used which indicates input translation. However, this was not implemented correctly, as for stage 2, the code only sets the S2 bit but not the IPA. This field has the same bits as FetchAddr in F_WALK_EABT which is populated correctly, so we don’t change that. The setting of this field should be done from the walker as the IPA address wouldn't be known in case of nesting. For stage 1, the spec says: If fault occurs at stage 1, S2 == 0 and: CLASS == IN, IPA is UNKNOWN. So, no need to set it to for stage 1, as ptw_info is initialised by zero in smmuv3_translate(). Fixes: e703f7076a “hw/arm/smmuv3: Add page table walk for stage-2” Reviewed-by: Jean-Philippe Brucker Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Message-id: 20240715084519.1189624-3-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 10 ++++++---- hw/arm/smmuv3.c | 4 ++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e81b684d06c..e8cdbcd8aef 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -448,7 +448,7 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, */ if (ipa >= (1ULL << inputsize)) { info->type = SMMU_PTW_ERR_TRANSLATION; - goto error; + goto error_ipa; } while (level < VMSA_LEVELS) { @@ -494,13 +494,13 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, */ if (!PTE_AF(pte) && !cfg->s2cfg.affd) { info->type = SMMU_PTW_ERR_ACCESS; - goto error; + goto error_ipa; } s2ap = PTE_AP(pte); if (is_permission_fault_s2(s2ap, perm)) { info->type = SMMU_PTW_ERR_PERMISSION; - goto error; + goto error_ipa; } /* @@ -509,7 +509,7 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, */ if (gpa >= (1ULL << cfg->s2cfg.eff_ps)) { info->type = SMMU_PTW_ERR_ADDR_SIZE; - goto error; + goto error_ipa; } tlbe->entry.translated_addr = gpa; @@ -522,6 +522,8 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, } info->type = SMMU_PTW_ERR_TRANSLATION; +error_ipa: + info->addr = ipa; error: info->stage = 2; tlbe->entry.perm = IOMMU_NONE; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 445e04ddf7c..cab545a0b46 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -949,6 +949,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, if (PTW_RECORD_FAULT(cfg)) { event.type = SMMU_EVT_F_TRANSLATION; event.u.f_translation.addr = addr; + event.u.f_translation.addr2 = ptw_info.addr; event.u.f_translation.rnw = flag & 0x1; } break; @@ -956,6 +957,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, if (PTW_RECORD_FAULT(cfg)) { event.type = SMMU_EVT_F_ADDR_SIZE; event.u.f_addr_size.addr = addr; + event.u.f_addr_size.addr2 = ptw_info.addr; event.u.f_addr_size.rnw = flag & 0x1; } break; @@ -963,6 +965,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, if (PTW_RECORD_FAULT(cfg)) { event.type = SMMU_EVT_F_ACCESS; event.u.f_access.addr = addr; + event.u.f_access.addr2 = ptw_info.addr; event.u.f_access.rnw = flag & 0x1; } break; @@ -970,6 +973,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, if (PTW_RECORD_FAULT(cfg)) { event.type = SMMU_EVT_F_PERMISSION; event.u.f_permission.addr = addr; + event.u.f_permission.addr2 = ptw_info.addr; event.u.f_permission.rnw = flag & 0x1; } break;