| Message ID | 20240717060903.205098-15-richard.henderson@linaro.org |
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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org,
qemu-stable@nongnu.org
Subject: [PATCH 14/17] target/arm: Clear high SVE elements in
handle_vec_simd_wshli
Date: Wed, 17 Jul 2024 16:09:00 +1000
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|
| Series |
target/arm: AdvSIMD decodetree conversion, part 4
|
expand
|
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index fd90752dee..d0ad6c90bc 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10471,6 +10471,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); write_vec_element(s, tcg_rd, rd, i, size + 1); } + clear_vec_high(s, true, rd); } /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
AdvSIMD instructions are supposed to zero bits beyond 128. Affects SSHLL, USHLL, SSHLL2, USHLL2. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/translate-a64.c | 1 + 1 file changed, 1 insertion(+)