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[209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6b5e80d6a09si48373146d6.90.2024.07.05.08.35.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Jul 2024 08:35:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GpVHWtY/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPku6-0005md-It; Fri, 05 Jul 2024 11:31:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPku4-0005kx-MW for qemu-devel@nongnu.org; Fri, 05 Jul 2024 11:31:16 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sPkty-0000SX-Ap for qemu-devel@nongnu.org; Fri, 05 Jul 2024 11:31:16 -0400 Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-a7523f0870cso210570566b.3 for ; Fri, 05 Jul 2024 08:31:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720193469; x=1720798269; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sv3Yug9NCQNk3EkRMmpkOBVsrQGJofWxvPFSJFd8Ubw=; b=GpVHWtY/10JPTQqo9fc5W80L2MzD5OWZGs/FeGydDNco5tw07T7Jq1OABijjp313g9 G645+jOJSpqNt5g7Oqx++mr40XEV7fuA8lFZohH0cmecqAP56iixmkzFfIL81zpJRo2R cyt75vKuqwJiPwepZQb+Cf8sra9S6TqQabTQytkyWKCxhM0KBwcLnmsmWbY5oSeE47Bm UEjHMAGomZbMi94iK8Ya2yOGo/in03yUeLON8vhZopefHDc74KYh7cmcqRNt5VFjXiig LAmJ240fdAnPbfMBA9dV7LpfV6lppUZw2GJGxFu/OTIFdXLTtiVun8pSL9qFEnIKlc0i 72JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720193469; x=1720798269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sv3Yug9NCQNk3EkRMmpkOBVsrQGJofWxvPFSJFd8Ubw=; b=bHjmz/AWym2T1F0vV/EyC1y2ubBq3p/eX3pKNn7MF5JYAPDvjkpecxUTiKLX+zYGMQ p2FSwIePVzT4E+8QyHhy61YDcyE0otbn2s9VYs1ySwqidHyBJLEwbK6CbpZQ6pgqezxH tFpJEsHAPMYq1Ae/1DlSNOWU3EUjur1JfNsYJJ/3+NMGm9slx+2zcZBel4Ntz3Ml+IMO 0eXGQu/YKPO5XfNNnnvhZboEpCFqg70GRGbEhok0qkWDdPiDNRwQTxc7669b6HmzU1Dl wfDcmih1MUZ1Yc6iQfhpWnxi8Ym3q/fg/2Fp3Xrw66TOOCl8K5mikwGWa3gS3nxIB7mf lOeQ== X-Gm-Message-State: AOJu0Yxkx/F+z8/P6b1I6GZKQXp8yU9JZ/W0aeYRsdg6Nnl5uxYvryMn fr8TtsTjf3KYoj3HUqtZ2wd021pRzMN/JCcG91f1xbUgngWn/zasYFiTe9hlRGA= X-Received: by 2002:a17:906:19c4:b0:a6f:33d6:2d45 with SMTP id a640c23a62f3a-a77ba708411mr273219266b.60.1720193468515; Fri, 05 Jul 2024 08:31:08 -0700 (PDT) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a72ae5ac5b8sm683287966b.14.2024.07.05.08.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jul 2024 08:31:06 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id DAE6C621B4; Fri, 5 Jul 2024 16:30:56 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , =?utf-8?q?Alex_Benn=C3=A9e?= , Paolo Bonzini , Thomas Huth , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 40/40] tests/tcg/aarch64: Add MTE gdbstub tests Date: Fri, 5 Jul 2024 16:30:52 +0100 Message-Id: <20240705153052.1219696-41-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240705153052.1219696-1-alex.bennee@linaro.org> References: <20240705153052.1219696-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gustavo Romero Add tests to exercise the MTE stubs. The tests will only run if a version of GDB that supports MTE is available in the test environment. Signed-off-by: Gustavo Romero [AJB: re-base and checkpatch fixes] Message-Id: <20240628050850.536447-12-gustavo.romero@linaro.org> Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-41-alex.bennee@linaro.org> diff --git a/configure b/configure index 8b6a2f16ce..019fcbd0ef 100755 --- a/configure +++ b/configure @@ -1673,6 +1673,10 @@ for target in $target_list; do echo "GDB=$gdb_bin" >> $config_target_mak fi + if test "${arch}" = "aarch64" && version_ge ${gdb_version##* } 15.0; then + echo "GDB_HAS_MTE=y" >> $config_target_mak + fi + echo "run-tcg-tests-$target: $qemu\$(EXESUF)" >> Makefile.prereqs tcg_tests_targets="$tcg_tests_targets $target" fi diff --git a/tests/tcg/aarch64/mte-8.c b/tests/tcg/aarch64/mte-8.c new file mode 100644 index 0000000000..808135ba43 --- /dev/null +++ b/tests/tcg/aarch64/mte-8.c @@ -0,0 +1,99 @@ +/* + * To be compiled with -march=armv8.5-a+memtag + * + * This test is adapted from a Linux test. Please see: + * + * https://www.kernel.org/doc/html/next/arch/arm64/memory-tagging-extension.html#example-of-correct-usage + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* + * From arch/arm64/include/uapi/asm/hwcap.h + */ +#define HWCAP2_MTE (1 << 18) + +/* + * From arch/arm64/include/uapi/asm/mman.h + */ +#define PROT_MTE 0x20 + +/* + * Insert a random logical tag into the given pointer. + */ +#define insert_random_tag(ptr) ({ \ + uint64_t __val; \ + asm("irg %0, %1" : "=r" (__val) : "r" (ptr)); \ + __val; \ +}) + +/* + * Set the allocation tag on the destination address. + */ +#define set_tag(tagged_addr) do { \ + asm volatile("stg %0, [%0]" : : "r" (tagged_addr) : "memory"); \ +} while (0) + + +int main(int argc, char *argv[]) +{ + unsigned char *a; + unsigned long page_sz = sysconf(_SC_PAGESIZE); + unsigned long hwcap2 = getauxval(AT_HWCAP2); + + /* check if MTE is present */ + if (!(hwcap2 & HWCAP2_MTE)) { + return EXIT_FAILURE; + } + + /* + * Enable the tagged address ABI, synchronous or asynchronous MTE + * tag check faults (based on per-CPU preference) and allow all + * non-zero tags in the randomly generated set. + */ + if (prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC | + (0xfffe << PR_MTE_TAG_SHIFT), + 0, 0, 0)) { + perror("prctl() failed"); + return EXIT_FAILURE; + } + + a = mmap(0, page_sz, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (a == MAP_FAILED) { + perror("mmap() failed"); + return EXIT_FAILURE; + } + + printf("a[] address is %p\n", a); + + /* + * Enable MTE on the above anonymous mmap. The flag could be passed + * directly to mmap() and skip this step. + */ + if (mprotect(a, page_sz, PROT_READ | PROT_WRITE | PROT_MTE)) { + perror("mprotect() failed"); + return EXIT_FAILURE; + } + + /* access with the default tag (0) */ + a[0] = 1; + a[1] = 2; + + printf("a[0] = %hhu a[1] = %hhu\n", a[0], a[1]); + + /* set the logical and allocation tags */ + a = (unsigned char *)insert_random_tag(a); + set_tag(a); + + printf("%p\n", a); + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index ad1774c2ce..b53218e115 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -64,7 +64,7 @@ AARCH64_TESTS += bti-2 # MTE Tests ifneq ($(CROSS_CC_HAS_ARMV8_MTE),) -AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 +AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-8 mte-%: CFLAGS += $(CROSS_CC_HAS_ARMV8_MTE) endif @@ -131,6 +131,18 @@ run-gdbstub-sve-ioctls: sve-ioctls basic gdbstub SVE ZLEN support) EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls + +ifeq ($(GDB_HAS_MTE),y) +run-gdbstub-mte: mte-8 + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-mte.py, \ + gdbstub MTE support) + +EXTRA_RUNS += run-gdbstub-mte +endif + endif endif diff --git a/tests/tcg/aarch64/gdbstub/test-mte.py b/tests/tcg/aarch64/gdbstub/test-mte.py new file mode 100644 index 0000000000..2db0663c1a --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-mte.py @@ -0,0 +1,86 @@ +from __future__ import print_function +# +# Test GDB memory-tag commands that exercise the stubs for the qIsAddressTagged, +# qMemTag, and QMemTag packets. Logical tag-only commands rely on local +# operations, hence don't exercise any stub. +# +# The test consists in breaking just after a atag() call (which sets the +# allocation tag -- see mte-8.c for details) and setting/getting tags in +# different memory locations and ranges starting at the address of the array +# 'a'. +# +# This is launched via tests/guest-debug/run-test.py +# + + +import gdb +import re +from test_gdbstub import main, report + + +PATTERN_0 = "Memory tags for address 0x[0-9a-f]+ match \(0x[0-9a-f]+\)." +PATTERN_1 = ".*(0x[0-9a-f]+)" + + +def run_test(): + gdb.execute("break 95", False, True) + gdb.execute("continue", False, True) + try: + # Test if we can check correctly that the allocation tag for + # array 'a' matches the logical tag after atag() is called. + co = gdb.execute("memory-tag check a", False, True) + tags_match = re.findall(PATTERN_0, co, re.MULTILINE) + if tags_match: + report(True, f"{tags_match[0]}") + else: + report(False, "Logical and allocation tags don't match!") + + # Test allocation tag 'set and print' commands. Commands on logical + # tags rely on local operation and so don't exercise any stub. + + # Set the allocation tag for the first granule (16 bytes) of + # address starting at 'a' address to a known value, i.e. 0x04. + gdb.execute("memory-tag set-allocation-tag a 1 04", False, True) + + # Then set the allocation tag for the second granule to a known + # value, i.e. 0x06. This tests that contiguous tag granules are + # set correct and don't run over each other. + gdb.execute("memory-tag set-allocation-tag a+16 1 06", False, True) + + # Read the known values back and check if they remain the same. + + co = gdb.execute("memory-tag print-allocation-tag a", False, True) + first_tag = re.match(PATTERN_1, co)[1] + + co = gdb.execute("memory-tag print-allocation-tag a+16", False, True) + second_tag = re.match(PATTERN_1, co)[1] + + if first_tag == "0x4" and second_tag == "0x6": + report(True, "Allocation tags are correctly set/printed.") + else: + report(False, "Can't set/print allocation tags!") + + # Now test fill pattern by setting a whole page with a pattern. + gdb.execute("memory-tag set-allocation-tag a 4096 0a0b", False, True) + + # And read back the tags of the last two granules in page so + # we also test if the pattern is set correctly up to the end of + # the page. + co = gdb.execute("memory-tag print-allocation-tag a+4096-32", False, True) + tag = re.match(PATTERN_1, co)[1] + + co = gdb.execute("memory-tag print-allocation-tag a+4096-16", False, True) + last_tag = re.match(PATTERN_1, co)[1] + + if tag == "0xa" and last_tag == "0xb": + report(True, "Fill pattern is ok.") + else: + report(False, "Fill pattern failed!") + + except gdb.error: + # This usually happens because a GDB version that does not + # support memory tagging was used to run the test. + report(False, "'memory-tag' command failed!") + + +main(run_test, expected_arch="aarch64")