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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 1/9] tcg: Introduce INDEX_op_plugin_pc Date: Wed, 5 Jun 2024 20:29:18 -0700 Message-Id: <20240606032926.83599-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add an opcode to find a code address within the current insn, for later use with unwinding. Generate the code generically using tcg_reg_alloc_do_movi. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- include/tcg/tcg-op-common.h | 1 + include/tcg/tcg-opc.h | 1 + tcg/tcg-op.c | 5 +++++ tcg/tcg.c | 10 ++++++++++ 4 files changed, 17 insertions(+) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 009e2778c5..a32c88a182 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -76,6 +76,7 @@ void tcg_gen_lookup_and_goto_ptr(void); void tcg_gen_plugin_cb(unsigned from); void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo); +void tcg_gen_plugin_pc(TCGv_ptr); /* 32 bit ops */ diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 546eb49c11..087d1b82da 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -199,6 +199,7 @@ DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT) DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT) +DEF(plugin_pc, 1, 0, 0, TCG_OPF_NOT_PRESENT) /* Replicate ld/st ops for 32 and 64-bit guest addresses. */ DEF(qemu_ld_a32_i32, 1, 1, 1, diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index eff3728622..b8ca78cbe4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -322,6 +322,11 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo) tcg_gen_op2(INDEX_op_plugin_mem_cb, tcgv_i64_arg(addr), meminfo); } +void tcg_gen_plugin_pc(TCGv_ptr arg) +{ + tcg_gen_op1(INDEX_op_plugin_pc, tcgv_ptr_arg(arg)); +} + /* 32 bit ops */ void tcg_gen_discard_i32(TCGv_i32 arg) diff --git a/tcg/tcg.c b/tcg/tcg.c index 34e3056380..b7c28d92a6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4689,6 +4689,13 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) } } +static void tcg_reg_alloc_plugin_pc(TCGContext *s, const TCGOp *op) +{ + tcg_reg_alloc_do_movi(s, arg_temp(op->args[0]), + (uintptr_t)tcg_splitwx_to_rx(s->code_ptr), + op->life, output_pref(op, 0)); +} + /* * Specialized code generation for INDEX_op_dup_vec. */ @@ -6196,6 +6203,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) case INDEX_op_mov_vec: tcg_reg_alloc_mov(s, op); break; + case INDEX_op_plugin_pc: + tcg_reg_alloc_plugin_pc(s, op); + break; case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break;