[PULL,18/38] target/sparc: Implement FPADD64, FPSUB64

Message ID	20240605172253.356302-19-richard.henderson@linaro.org
State	Accepted
Commit	bc3f14a9ed777ddab8c8915a9804f9b3ca90839d
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL 18/38] target/sparc: Implement FPADD64, FPSUB64 Date: Wed, 5 Jun 2024 10:22:33 -0700 Message-Id: <20240605172253.356302-19-richard.henderson@linaro.org> In-Reply-To: <20240605172253.356302-1-richard.henderson@linaro.org> References: <20240605172253.356302-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/38] linux-user: Add ioctl for BLKBSZSET \| expand [PULL,01/38] linux-user: Add ioctl for BLKBSZSET [PULL,02/38] target/sparc: Fix ARRAY8 [PULL,03/38] target/sparc: Rewrite gen_edge [PULL,04/38] target/sparc: Fix do_dc [PULL,05/38] target/sparc: Fix helper_fmul8ulx16 [PULL,06/38] target/sparc: Perform DFPREG/QFPREG in decodetree [PULL,07/38] target/sparc: Remove gen_dest_fpr_D [PULL,08/38] target/sparc: Remove cpu_fpr[] [PULL,09/38] target/sparc: Use gvec for VIS1 parallel add/sub [PULL,10/38] target/sparc: Implement FMAf extension [PULL,11/38] target/sparc: Add feature bits for VIS 3 [PULL,12/38] target/sparc: Implement ADDXC, ADDXCcc [PULL,13/38] target/sparc: Implement CMASK instructions [PULL,14/38] target/sparc: Implement FCHKSM16 [PULL,15/38] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL [PULL,16/38] target/sparc: Implement FLCMP [PULL,17/38] target/sparc: Implement FMEAN16 [PULL,18/38] target/sparc: Implement FPADD64, FPSUB64 [PULL,19/38] target/sparc: Implement FPADDS, FPSUBS [PULL,20/38] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 [PULL,21/38] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS [PULL,22/38] target/sparc: Implement LDXEFSR [PULL,23/38] target/sparc: Implement LZCNT [PULL,24/38] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd [PULL,25/38] target/sparc: Implement PDISTN [PULL,26/38] target/sparc: Implement UMULXHI [PULL,27/38] target/sparc: Implement XMULX [PULL,28/38] target/sparc: Enable VIS3 feature bit [PULL,29/38] target/sparc: Implement IMA extension [PULL,30/38] target/sparc: Add feature bit for VIS4 [PULL,31/38] target/sparc: Implement FALIGNDATAi [PULL,32/38] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS [PULL,33/38] target/sparc: Implement VIS4 comparisons [PULL,34/38] target/sparc: Implement FPMIN, FPMAX [PULL,35/38] target/sparc: Implement SUBXC, SUBXCcc [PULL,36/38] target/sparc: Implement MWAIT [PULL,37/38] target/sparc: Implement monitor ASIs [PULL,38/38] target/sparc: Enable VIS4 feature bit

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20240605172253.356302-19-richard.henderson@linaro.org

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Accepted

Commit

bc3f14a9ed777ddab8c8915a9804f9b3ca90839d

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Subject: [PULL 18/38] target/sparc: Implement FPADD64, FPSUB64
Date: Wed,  5 Jun 2024 10:22:33 -0700
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Series

[PULL,01/38] linux-user: Add ioctl for BLKBSZSET | expand

Commit Message

Richard Henderson June 5, 2024, 5:22 p.m. UTC

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/insns.decode | 2 ++
 target/sparc/translate.c  | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index febd1a4a13..70ca41a69a 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -441,10 +441,12 @@  FCMPEq      10 000 cc:2 110101 .....  0 0101 0111 .....    \
     FPADD16s    10 ..... 110110 ..... 0 0101 0001 .....    @r_r_r
     FPADD32     10 ..... 110110 ..... 0 0101 0010 .....    @d_d_d
     FPADD32s    10 ..... 110110 ..... 0 0101 0011 .....    @r_r_r
+    FPADD64     10 ..... 110110 ..... 0 0100 0010 .....    @d_d_d
     FPSUB16     10 ..... 110110 ..... 0 0101 0100 .....    @d_d_d
     FPSUB16s    10 ..... 110110 ..... 0 0101 0101 .....    @r_r_r
     FPSUB32     10 ..... 110110 ..... 0 0101 0110 .....    @d_d_d
     FPSUB32s    10 ..... 110110 ..... 0 0101 0111 .....    @r_r_r
+    FPSUB64     10 ..... 110110 ..... 0 0100 0110 .....    @d_d_d
 
     FNORd       10 ..... 110110 ..... 0 0110 0010 .....    @d_d_d
     FNORs       10 ..... 110110 ..... 0 0110 0011 .....    @r_r_r
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index c3956f489b..48cab59c07 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4912,6 +4912,9 @@  TRANS(FHADDd, VIS3, do_ddd, a, gen_op_fhaddd)
 TRANS(FHSUBd, VIS3, do_ddd, a, gen_op_fhsubd)
 TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd)
 
+TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64)
+TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64)
+
 static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
                    void (*func)(TCGv, TCGv_i64, TCGv_i64))
 {

[PULL,18/38] target/sparc: Implement FPADD64, FPSUB64

Commit Message

Patch