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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c967cd2sm101704155ad.166.2024.05.29.10.36.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 10:36:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH RISU] risugen/arm: Refine prefetch and memory hintspace patterns Date: Wed, 29 May 2024 10:36:25 -0700 Message-Id: <20240529173625.800102-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Avoid prefetch patterns that are UNPREDICTABLE. Signed-off-by: Richard Henderson --- thumb.risu | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/thumb.risu b/thumb.risu index 357b791..6a05bf2 100644 --- a/thumb.risu +++ b/thumb.risu @@ -33,7 +33,20 @@ SMMUL T1 11111 0110 101 rn:4 1111 rd:4 000 r rm:4 # preload and memory hint space (in the byte and halfword # load space, where Rt == 15). # The constraint is to avoid UNPREDICTABLE space -HINTSPACE T1 111 1100 op1:2 0 z 1 y:4 1111 op2:6 any:6 { ($y == 15) || (($op1 & 1) != 0) || !((($op2 & 0x24) == 0x24) || (($op2 & 0x3c) == 0x38)) ; } +PLD_pi TI 1111 1000 10 w 1 rn:4 1111 imm:12 { $rn != 0xf; } +PLD_ni TI 1111 1000 00 w 1 rn:4 1111 1100 imm:8 { $rn != 0xf; } +PLD_li TI 1111 1000 u 00 1 1111 1111 imm:12 +PLD_rr TI 1111 1000 00 w 1 rn:4 1111 000000 imm:2 rm:4 \ + { $rn != 0xf && $rm != 0xf; } +PLI_pi TI 1111 1001 1 00 1 rn:4 1111 imm:12 { $rn != 0xf; } +PLI_ni TI 1111 1001 0 00 1 rn:4 1111 1100 imm:8 { $rn != 0xf; } +PLI_li TI 1111 1001 u 00 1 1111 1111 imm:12 +PLI_rr TI 1111 1001 0 00 1 rn:4 1111 000000 imm:2 rm:4 \ + { $rn != 0xf && $rm != 0xf; } +HINTSPACE_rr T1 1111 1001 0011 rn:4 1111 000000 imm:2 rm:4 { $rn != 0xf; } +HINTSPACE_ni T1 1111 1001 0011 rn:4 1111 1100 imm:8 { $rn != 0xf; } +HINTSPACE_pi T1 1111 1001 1011 rn:4 1111 imm:12 { $rn != 0xf; } +HINTSPACE_li T1 1111 1001 u 011 1111 1111 imm:12 # VMLAL, VMLSL, VQDMLAL, VQDMLSL, VMULL, VQDMULL # NB that enc T1 is actually VMLA/VMLS only, T2 is VMLAL/VMLSL only