From patchwork Tue May 28 20:30:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 799511 Delivered-To: patch@linaro.org Received: by 2002:adf:e110:0:b0:35b:5a80:51b4 with SMTP id t16csp421669wrz; Tue, 28 May 2024 13:33:04 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV2waSWsGeQor8ENG9l5Ghvn8abhzAr4m/OIEzGmAoHgJ3K+C4YhGnj9oJCWPbaoUDiMs8tzY37keUl6duA+tge X-Google-Smtp-Source: AGHT+IHezwrXFR3JSbj9mMh78eXt9/0UDrLphZRR5bHSA+fIlVNAPib48dFjd1/sD6kwUQImc0hZ X-Received: by 2002:a05:6214:4342:b0:6ab:9884:1a82 with SMTP id 6a1803df08f44-6abcd0d4bbfmr159533306d6.51.1716928383815; Tue, 28 May 2024 13:33:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1716928383; cv=none; d=google.com; s=arc-20160816; b=wvq7NIeblHzIjbzILoBe1YFPpocaZo8QI9dI03iej+OsPkhrvrFRadrt1gE1kLbzeL sM1RSs+NcYiBPJq3p6TBkSBvzjDmfi7ycOxw2QaUHAvRFIDdnL99W+KJCGsos6TRD/M3 aEHz4yFG/H2DfqpKFWsh4jERYK5Qy73jM3RnRvp7LTpa2+R9Wq+rPri2fhCnsdtj6hn4 w1oK9926p5Jf7sen079vj5q2Uj/7GkB/mB9dTxfRJN6WKq1Y8q3vKLueZmIckjOrLo/P eHqwnae9xVi5rnT80m1Finpz+9cuNK4qHjNfuiXL2Uv8ymk5S0GeOCLvGCsYbd6nC1W8 laJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PIsDasQwFl6FIiAk8sxwPdmrhXfZIJdN9zLl0SzK5sE=; fh=ZhBia3nL9o1nuf7SbgdYn/0pDmAeja6gisyWXi2cqYE=; b=NTdVuvGS3TXYgcj/sj0bTQHDdjKoS9VmmviJOZgthcTV16mfE+xJz5mm2lalIjJivh odnlAxwEj9GGw/L+UbZZtaZyX6I2ITmsuN2f40Wd+GdP5S9KYgEYDx8oPFpgH0dzTlk1 klPZ6PRUYiIU4NzvwaXg1JMScHJHYCGnd+WHUtClUGLI/TzKYtchusO8Kv98bPdbzDJH ujAlZUzP5pCDwZoL92vpU+o44KiPlCLclOCs1AkJOmYdGpZafuChatxw5RsQxKaGDsVC 2HMCWK3mudWGvYp8B2WZ5VU7sEYNwDnxFVd+j7jpckCC/IYGo81fGtl1NUtssIUDqN7f 5CqA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QVlZK2gn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6ac0707e4c6si114128426d6.128.2024.05.28.13.33.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 May 2024 13:33:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QVlZK2gn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sC3Tk-00037N-5M; Tue, 28 May 2024 16:31:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sC3TR-0002qz-4I for qemu-devel@nongnu.org; Tue, 28 May 2024 16:31:09 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sC3TB-0003aF-It for qemu-devel@nongnu.org; Tue, 28 May 2024 16:31:08 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6f8edff35a0so1097360b3a.2 for ; Tue, 28 May 2024 13:30:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716928252; x=1717533052; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PIsDasQwFl6FIiAk8sxwPdmrhXfZIJdN9zLl0SzK5sE=; b=QVlZK2gnqYyVTkiiNwx3sQmxazz/Q3ehDXPtB5KAwmZG8ULiT5DnK2tCkihCyyYtWd UJTuwVSR+RG/iBfapDJ9WepMxVX+zxKFF7OVaL79th74MpPMDdJkga7aacF2lCvor40j RqlBcDC6Q9GHoTyL8fmXlQK7S/FjwrTaKYnDVglllLwcPm8BnaG1BZkADX5Zapt3o5BC UyyrDhvrFSmtM08rQJbPH9O+cihG2VOVnVjAo2BwQg2LlyZ19ZirFTRJmS7Ke3pkNnVa qeIFQS9iDPG4NEiMCFzhwZdK3tWT7mu/dJFoKw8dazUXk+JELryBTSxpFCMWPkZwTIOs +kvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716928252; x=1717533052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PIsDasQwFl6FIiAk8sxwPdmrhXfZIJdN9zLl0SzK5sE=; b=M681iLug+6pTnUvYYttBvZFrlqKWD+iaK37t6P+XMkhgLh6VPvMYEJnheHeqmDOI3t h9YY3dSvE1lDVk48Oz2+UezQDStDxnLayq/XCMRBkZz9eiMT14RXbdVCcPlawah9LAud vzXykPRyTJsyvr+wSkav3er6qDLOqNWW4PSU6oKra1tWjqqsijQ4MhXB7mdDYjAcNwDt 4mDbVWsiWBfp7hAgTKSGHK3QwW09QudHwjlbSFlgU+DovrF4uyT91P7Vf7ihdFiwSCwu JIHjshVhbjNYDfjoc9jjXUdcp1HEnzjXzIRDhjp8of0cNDciOC5mnZgt5HieVRB/tq+I ekGA== X-Gm-Message-State: AOJu0Yz+gg5xQq82LzoTTlDssKaTq7qJKf8oRtr3EDdc4V1JkegaOBVu cPi8ossTQ6D+iebK3J6JHO3NFzpY9kc3c1xM2U6LSCflALPdDmfP6vyI6R20SxHqKKwLdgzSgKq k X-Received: by 2002:a05:6a00:6516:b0:701:e5f5:9f8e with SMTP id d2e1a72fcca58-701e5f5a2e4mr1444531b3a.16.1716928251975; Tue, 28 May 2024 13:30:51 -0700 (PDT) Received: from stoup.. (174-21-72-5.tukw.qwest.net. [174.21.72.5]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fbd3dbe9sm7042036b3a.10.2024.05.28.13.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 13:30:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 07/33] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree Date: Tue, 28 May 2024 13:30:18 -0700 Message-Id: <20240528203044.612851-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240528203044.612851-1-richard.henderson@linaro.org> References: <20240528203044.612851-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 11 ++++ target/arm/tcg/translate-a64.c | 96 +++++++++++++++++++--------------- 2 files changed, 64 insertions(+), 43 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index f48adef5bb..19010af03b 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -44,6 +44,7 @@ @rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 @rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd @rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd +@rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e @rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm @rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl @@ -744,6 +745,11 @@ FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd +SQADD_s 0101 1110 ..1 ..... 00001 1 ..... ..... @rrr_e +UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e +SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e +UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e + ### Advanced SIMD scalar pairwise FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h @@ -857,6 +863,11 @@ BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b +SQADD_v 0.00 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e +UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e +SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e +UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e + ### Advanced SIMD scalar x indexed element FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ca7ba6b1e8..3956c41543 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5060,6 +5060,43 @@ static const FPScalar f_scalar_frsqrts = { }; TRANS(FRSQRTS_s, do_fp3_scalar, a, &f_scalar_frsqrts) +static bool do_satacc_s(DisasContext *s, arg_rrr_e *a, + MemOp sgn_n, MemOp sgn_m, + void (*gen_bhs)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, MemOp), + void (*gen_d)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 t0, t1, t2, qc; + MemOp esz = a->esz; + + if (!fp_access_check(s)) { + return true; + } + + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + qc = tcg_temp_new_i64(); + read_vec_element(s, t1, a->rn, 0, esz | sgn_n); + read_vec_element(s, t2, a->rm, 0, esz | sgn_m); + tcg_gen_ld_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc)); + + if (esz == MO_64) { + gen_d(t0, qc, t1, t2); + } else { + gen_bhs(t0, qc, t1, t2, esz); + tcg_gen_ext_i64(t0, t0, esz); + } + + write_fp_dreg(s, a->rd, t0); + tcg_gen_st_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc)); + return true; +} + +TRANS(SQADD_s, do_satacc_s, a, MO_SIGN, MO_SIGN, gen_sqadd_bhs, gen_sqadd_d) +TRANS(SQSUB_s, do_satacc_s, a, MO_SIGN, MO_SIGN, gen_sqsub_bhs, gen_sqsub_d) +TRANS(UQADD_s, do_satacc_s, a, 0, 0, gen_uqadd_bhs, gen_uqadd_d) +TRANS(UQSUB_s, do_satacc_s, a, 0, 0, gen_uqsub_bhs, gen_uqsub_d) + static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a, gen_helper_gvec_3_ptr * const fns[3]) { @@ -5298,6 +5335,11 @@ TRANS(BSL_v, do_bitsel, a->q, a->rd, a->rd, a->rn, a->rm) TRANS(BIT_v, do_bitsel, a->q, a->rd, a->rm, a->rn, a->rd) TRANS(BIF_v, do_bitsel, a->q, a->rd, a->rm, a->rd, a->rn) +TRANS(SQADD_v, do_gvec_fn3, a, gen_gvec_sqadd_qc) +TRANS(UQADD_v, do_gvec_fn3, a, gen_gvec_uqadd_qc) +TRANS(SQSUB_v, do_gvec_fn3, a, gen_gvec_sqsub_qc) +TRANS(UQSUB_v, do_gvec_fn3, a, gen_gvec_uqsub_qc) + /* * Advanced SIMD scalar/vector x indexed element */ @@ -9291,29 +9333,8 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, * or scalar-three-reg-same groups. */ TCGCond cond; - TCGv_i64 qc; switch (opcode) { - case 0x1: /* SQADD */ - qc = tcg_temp_new_i64(); - tcg_gen_ld_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc)); - if (u) { - gen_uqadd_d(tcg_rd, qc, tcg_rn, tcg_rm); - } else { - gen_sqadd_d(tcg_rd, qc, tcg_rn, tcg_rm); - } - tcg_gen_st_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc)); - break; - case 0x5: /* SQSUB */ - qc = tcg_temp_new_i64(); - tcg_gen_ld_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc)); - if (u) { - gen_uqsub_d(tcg_rd, qc, tcg_rn, tcg_rm); - } else { - gen_sqsub_d(tcg_rd, qc, tcg_rn, tcg_rm); - } - tcg_gen_st_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc)); - break; case 0x6: /* CMGT, CMHI */ cond = u ? TCG_COND_GTU : TCG_COND_GT; do_cmop: @@ -9366,6 +9387,8 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, } break; default: + case 0x1: /* SQADD / UQADD */ + case 0x5: /* SQSUB / UQSUB */ g_assert_not_reached(); } } @@ -9387,8 +9410,6 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) TCGv_i64 tcg_rd; switch (opcode) { - case 0x1: /* SQADD, UQADD */ - case 0x5: /* SQSUB, UQSUB */ case 0x9: /* SQSHL, UQSHL */ case 0xb: /* SQRSHL, UQRSHL */ break; @@ -9410,6 +9431,8 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) } break; default: + case 0x1: /* SQADD, UQADD */ + case 0x5: /* SQSUB, UQSUB */ unallocated_encoding(s); return; } @@ -9436,12 +9459,6 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) void (*genfn)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, MemOp) = NULL; switch (opcode) { - case 0x1: /* SQADD, UQADD */ - genfn = u ? gen_uqadd_bhs : gen_sqadd_bhs; - break; - case 0x5: /* SQSUB, UQSUB */ - genfn = u ? gen_uqsub_bhs : gen_sqsub_bhs; - break; case 0x9: /* SQSHL, UQSHL */ { static NeonGenTwoOpEnvFn * const fns[3][2] = { @@ -9473,6 +9490,8 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) break; } default: + case 0x1: /* SQADD, UQADD */ + case 0x5: /* SQSUB, UQSUB */ g_assert_not_reached(); } @@ -10933,6 +10952,11 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) return; } break; + + case 0x01: /* SQADD, UQADD */ + case 0x05: /* SQSUB, UQSUB */ + unallocated_encoding(s); + return; } if (!fp_access_check(s)) { @@ -10940,20 +10964,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } switch (opcode) { - case 0x01: /* SQADD, UQADD */ - if (u) { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqadd_qc, size); - } else { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqadd_qc, size); - } - return; - case 0x05: /* SQSUB, UQSUB */ - if (u) { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqsub_qc, size); - } else { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqsub_qc, size); - } - return; case 0x08: /* SSHL, USHL */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_ushl, size);