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[209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6ac06f4eeafsi105311746d6.8.2024.05.28.08.02.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 May 2024 08:02:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Czex2/t8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sByJL-0000eZ-1M; Tue, 28 May 2024 11:00:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sByJE-0000e8-NK for qemu-devel@nongnu.org; Tue, 28 May 2024 11:00:16 -0400 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sByJC-000759-Mk for qemu-devel@nongnu.org; Tue, 28 May 2024 11:00:16 -0400 Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-52388d9ca98so1604696e87.0 for ; Tue, 28 May 2024 08:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716908412; x=1717513212; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wQcbwizGTPGLe0I7sDsQyBs7g4DJMYLbmLP09XmJRR0=; b=Czex2/t8O7se/uXPr0z5QwXQFhYB8DeINFLrTEKcaT90yNsZm7idmEurYh4WEqAJpX jMfr1l0uNx8mKEI4UYmQjreeuAjJTgDzxlLJH/MPw4ATrPoFybMn3ap2lHAUaB1CsCz0 DktJDTOIwSiZQVsBDzD/IXfXJZQvuGjQHS3HKJSP0laHELWCIo4LAsyjfH7CLmOhUErk DFSyHL+R5vXxwLUFjtRfQZnIzrXvnZREHjO7RIqX3JFcjASXqROksFYEKZD+mA9OlE4A 8QZPPxwLEi/NsehS+MD6U0N19fmmqNFGQCFaOqIJwGRKrnzqJdoGYENFfwrE58+BAzxq ru9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716908412; x=1717513212; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wQcbwizGTPGLe0I7sDsQyBs7g4DJMYLbmLP09XmJRR0=; b=Zrov4+S00WfkrnPhn+UJTRsOiFC6JDAsb2eEwQqvVAoczT0O2GQq45SQ18Zw0ySkFD ejwSjX7meGAkKalVbSKNV50PyjCoMReqTfi7nrcaQt8fBV8d24v6iaOzjcU2LiVqyemF yljwaW68gWD+JqOzwnsn18xXgdTbxg/o5GbPQC8tRTtbC0jErGYtiDfms0uCsD6WBmuf ounJOVWzu7bHQ2Y1ajV0FLcOr3DV+shsQcoWN7q808MWDuEq7GNBGaioaq3dmkUy/8gc Uj6p4npXbFHYUSv2mgzjRKe//udPuBKOV+1GhaYNYARn8a2wTxIhPN6cX8q5AibXUPvd qO1Q== X-Gm-Message-State: AOJu0Yz9akHzZfZyGrFgdh6jD8WPlHtZDic0elHdaV3FGtYWvxAEKrU4 AcAZG+6tTIIZCR/b02b77hXEJ5vVfT1VmzAAqTAO3ep8INnZHF8Igk18/sXHDTU2yTAik6AOPfs A X-Received: by 2002:ac2:46e2:0:b0:51f:4d57:6812 with SMTP id 2adb3069b0e04-5296594cfc7mr9627468e87.19.1716908412379; Tue, 28 May 2024 08:00:12 -0700 (PDT) Received: from m1x-phil.lan ([176.187.214.26]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626cd9fed2sm622256666b.187.2024.05.28.08.00.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 May 2024 08:00:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Paolo Bonzini , Richard Henderson Subject: [PATCH 3/6] accel: Clarify accel_cpu_common_[un]realize() use unassigned vCPU Date: Tue, 28 May 2024 16:59:49 +0200 Message-ID: <20240528145953.65398-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240528145953.65398-1-philmd@linaro.org> References: <20240528145953.65398-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philmd@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation of introducing [un]realize handlers for when vCPUs are assigned, rename current handlers using the '_unassigned' suffix. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/internal-common.h | 4 ++-- include/qemu/accel.h | 17 +++++++++++------ accel/accel-target.c | 11 ++++++----- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/tcg-all.c | 4 ++-- cpu-target.c | 4 ++-- 6 files changed, 25 insertions(+), 19 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index a8fc3db774..ec2c6317b7 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -53,7 +53,7 @@ TranslationBlock *tb_link_page(TranslationBlock *tb); void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc); -bool tcg_exec_realizefn(CPUState *cpu, Error **errp); -void tcg_exec_unrealizefn(CPUState *cpu); +bool tcg_exec_realize_unassigned(CPUState *cpu, Error **errp); +void tcg_exec_unrealize_unassigned(CPUState *cpu); #endif diff --git a/include/qemu/accel.h b/include/qemu/accel.h index 972a849a2b..dd18c41dc0 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -43,8 +43,8 @@ typedef struct AccelClass { bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); #endif - bool (*cpu_common_realize)(CPUState *cpu, Error **errp); - void (*cpu_common_unrealize)(CPUState *cpu); + bool (*cpu_common_realize_unassigned)(CPUState *cpu, Error **errp); + void (*cpu_common_unrealize_unassigned)(CPUState *cpu); /* gdbstub related hooks */ int (*gdbstub_supported_sstep_flags)(void); @@ -92,17 +92,22 @@ void accel_setup_post(MachineState *ms); void accel_cpu_instance_init(CPUState *cpu); /** - * accel_cpu_common_realize: + * accel_cpu_common_realize_unassigned: * @cpu: The CPU that needs to call accel-specific cpu realization. * @errp: currently unused. + * + * The @cpu index is not yet assigned. */ -bool accel_cpu_common_realize(CPUState *cpu, Error **errp); +bool accel_cpu_common_realize_unassigned(CPUState *cpu, Error **errp); /** - * accel_cpu_common_unrealize: + * accel_cpu_common_unrealize_unassigned: * @cpu: The CPU that needs to call accel-specific cpu unrealization. + * + * The @cpu index is no more assigned, @cpu has been removed from the global + * #cpus_queue. */ -void accel_cpu_common_unrealize(CPUState *cpu); +void accel_cpu_common_unrealize_unassigned(CPUState *cpu); /** * accel_supported_gdbstub_sstep_flags: diff --git a/accel/accel-target.c b/accel/accel-target.c index 08626c00c2..e0a79c0fce 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -119,7 +119,7 @@ void accel_cpu_instance_init(CPUState *cpu) } } -bool accel_cpu_common_realize(CPUState *cpu, Error **errp) +bool accel_cpu_common_realize_unassigned(CPUState *cpu, Error **errp) { CPUClass *cc = CPU_GET_CLASS(cpu); AccelState *accel = current_accel(); @@ -132,21 +132,22 @@ bool accel_cpu_common_realize(CPUState *cpu, Error **errp) } /* generic realization */ - if (acc->cpu_common_realize && !acc->cpu_common_realize(cpu, errp)) { + if (acc->cpu_common_realize_unassigned + && !acc->cpu_common_realize_unassigned(cpu, errp)) { return false; } return true; } -void accel_cpu_common_unrealize(CPUState *cpu) +void accel_cpu_common_unrealize_unassigned(CPUState *cpu) { AccelState *accel = current_accel(); AccelClass *acc = ACCEL_GET_CLASS(accel); /* generic unrealization */ - if (acc->cpu_common_unrealize) { - acc->cpu_common_unrealize(cpu); + if (acc->cpu_common_unrealize_unassigned) { + acc->cpu_common_unrealize_unassigned(cpu); } } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2972f75b96..08769cf91e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1074,7 +1074,7 @@ int cpu_exec(CPUState *cpu) return ret; } -bool tcg_exec_realizefn(CPUState *cpu, Error **errp) +bool tcg_exec_realize_unassigned(CPUState *cpu, Error **errp) { static bool tcg_target_initialized; @@ -1094,7 +1094,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) } /* undo the initializations in reverse order */ -void tcg_exec_unrealizefn(CPUState *cpu) +void tcg_exec_unrealize_unassigned(CPUState *cpu) { #ifndef CONFIG_USER_ONLY tcg_iommu_free_notifier_list(cpu); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 2090907dba..c08a6acc21 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -227,8 +227,8 @@ static void tcg_accel_class_init(ObjectClass *oc, void *data) AccelClass *ac = ACCEL_CLASS(oc); ac->name = "tcg"; ac->init_machine = tcg_init_machine; - ac->cpu_common_realize = tcg_exec_realizefn; - ac->cpu_common_unrealize = tcg_exec_unrealizefn; + ac->cpu_common_realize_unassigned = tcg_exec_realize_unassigned; + ac->cpu_common_unrealize_unassigned = tcg_exec_unrealize_unassigned; ac->allowed = &tcg_allowed; ac->gdbstub_supported_sstep_flags = tcg_gdbstub_supported_sstep_flags; diff --git a/cpu-target.c b/cpu-target.c index 5af120e8aa..9ab5a28cb5 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -136,7 +136,7 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp) /* cache the cpu class for the hotpath */ cpu->cc = CPU_GET_CLASS(cpu); - if (!accel_cpu_common_realize(cpu, errp)) { + if (!accel_cpu_common_realize_unassigned(cpu, errp)) { return false; } @@ -176,7 +176,7 @@ void cpu_exec_unrealizefn(CPUState *cpu) * Now that the vCPU has been removed from the RCU list, we can call * accel_cpu_common_unrealize, which may free fields using call_rcu. */ - accel_cpu_common_unrealize(cpu); + accel_cpu_common_unrealize_unassigned(cpu); } /*