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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2bf5f6155b6sm4943761a91.29.2024.05.26.12.36.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:36:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH RISU v2 08/13] sparc64: Add a few logical insns Date: Sun, 26 May 2024 12:36:32 -0700 Message-Id: <20240526193637.459064-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526193637.459064-1-richard.henderson@linaro.org> References: <20240526193637.459064-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Just a token to verify the script is working. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- sparc64.risu | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 sparc64.risu diff --git a/sparc64.risu b/sparc64.risu new file mode 100644 index 0000000..b45ea86 --- /dev/null +++ b/sparc64.risu @@ -0,0 +1,30 @@ +############################################################################### +# Copyright (c) 2024 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +############################################################################### + +# Input file for risugen defining Sparc64 instructions +.mode sparc64 + +ADD_r SPARC 10 rd:5 0 cc:1 ci:1 000 rs1:5 0 00000000 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +ADD_i SPARC 10 rd:5 0 cc:1 ci:1 000 rs1:5 1 imm:13 \ + !constraints { reg_ok($rd) && reg_ok($rs1); } + +AND_r SPARC 10 rd:5 0 cc:1 0001 rs1:5 0 00000000 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +AND_i SPARC 10 rd:5 0 cc:1 0001 rs1:5 1 imm:13 \ + !constraints { reg_ok($rd) && reg_ok($rs1); } + +OR_r SPARC 10 rd:5 0 cc:1 0010 rs1:5 0 00000000 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +OR_i SPARC 10 rd:5 0 cc:1 0010 rs1:5 1 imm:13 \ + !constraints { reg_ok($rd) && reg_ok($rs1); } + +XOR_r SPARC 10 rd:5 0 cc:1 0011 rs1:5 0 00000000 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +XOR_i SPARC 10 rd:5 0 cc:1 0011 rs1:5 1 imm:13 \ + !constraints { reg_ok($rd) && reg_ok($rs1); }