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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2bf5f6155b6sm4943761a91.29.2024.05.26.12.36.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:36:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH RISU v2 10/13] sparc64: Add VIS2 and FMAF insns Date: Sun, 26 May 2024 12:36:34 -0700 Message-Id: <20240526193637.459064-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526193637.459064-1-richard.henderson@linaro.org> References: <20240526193637.459064-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- sparc64.risu | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index 10a8510..5b90b70 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -119,3 +119,39 @@ FEXPAND VIS1 10 rd:5 110110 00000 0 0100 1101 rs2:5 # ALIGNADDRL VIS1 10 rd:5 110110 rs1:5 0 0001 1010 rs2:5 \ # !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } # FALIGNDATAg VIS1 10 rd:5 110110 rs1:5 0 0100 1000 rs2:5 + +# +# VIS2 +# + +EDGE8N VIS2 10 rd:5 110110 rs1:5 0 0000 0001 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +EDGE8LN VIS2 10 rd:5 110110 rs1:5 0 0000 0011 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +EDGE16N VIS2 10 rd:5 110110 rs1:5 0 0000 0101 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +EDGE16LN VIS2 10 rd:5 110110 rs1:5 0 0000 0111 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +EDGE32N VIS2 10 rd:5 110110 rs1:5 0 0000 1001 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +EDGE32LN VIS2 10 rd:5 110110 rs1:5 0 0000 1011 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } + +# %gsr not handled by risu +# BMASK VIS2 10 rd:5 110110 rs1:5 0 0001 1001 rs2:5 \ +# !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +# BSHUFFLE VIS2 10 rd:5 110110 rs1:5 0 0100 1100 rs2:5 +# SIAM VIS2 10 00000 110110 00000 010000001 00 mode:3 + +# +# FMAF +# + +FMADDs FMAF 10 rd:5 110111 rs1:5 rs3:5 0001 rs2:5 +FMADDd FMAF 10 rd:5 110111 rs1:5 rs3:5 0010 rs2:5 +FMSUBs FMAF 10 rd:5 110111 rs1:5 rs3:5 0101 rs2:5 +FMSUBd FMAF 10 rd:5 110111 rs1:5 rs3:5 0110 rs2:5 +FNMSUBs FMAF 10 rd:5 110111 rs1:5 rs3:5 1001 rs2:5 +FNMSUBd FMAF 10 rd:5 110111 rs1:5 rs3:5 1010 rs2:5 +FNMADDs FMAF 10 rd:5 110111 rs1:5 rs3:5 1101 rs2:5 +FNMADDd FMAF 10 rd:5 110111 rs1:5 rs3:5 1110 rs2:5