@@ -24,6 +24,7 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
#include "qemu/interval-tree.h"
+#include "hw/registerfields.h"
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
@@ -158,6 +159,30 @@
#define CR_IPSW 22
#define CR_EIRR 23
+FIELD(FPSR, ENA_I, 0, 1)
+FIELD(FPSR, ENA_U, 1, 1)
+FIELD(FPSR, ENA_O, 2, 1)
+FIELD(FPSR, ENA_Z, 3, 1)
+FIELD(FPSR, ENA_V, 4, 1)
+FIELD(FPSR, ENABLES, 0, 5)
+FIELD(FPSR, D, 5, 1)
+FIELD(FPSR, T, 6, 1)
+FIELD(FPSR, RM, 9, 2)
+FIELD(FPSR, CQ, 11, 11)
+FIELD(FPSR, CQ0_6, 15, 7)
+FIELD(FPSR, CQ0_4, 17, 5)
+FIELD(FPSR, CQ0_2, 19, 3)
+FIELD(FPSR, CQ0, 21, 1)
+FIELD(FPSR, CA, 15, 7)
+FIELD(FPSR, CA0, 21, 1)
+FIELD(FPSR, C, 26, 1)
+FIELD(FPSR, FLG_I, 27, 1)
+FIELD(FPSR, FLG_U, 28, 1)
+FIELD(FPSR, FLG_O, 29, 1)
+FIELD(FPSR, FLG_Z, 30, 1)
+FIELD(FPSR, FLG_V, 31, 1)
+FIELD(FPSR, FLAGS, 27, 5)
+
typedef struct HPPATLBEntry {
union {
IntervalTreeNode itree;
@@ -30,7 +30,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
env->fr0_shadow = shadow;
- switch (extract32(shadow, 9, 2)) {
+ switch (FIELD_EX32(shadow, FPSR, RM)) {
default:
rm = float_round_nearest_even;
break;
@@ -46,7 +46,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
}
set_float_rounding_mode(rm, &env->fp_status);
- d = extract32(shadow, 5, 1);
+ d = FIELD_EX32(shadow, FPSR, D);
set_flush_to_zero(d, &env->fp_status);
set_flush_inputs_to_zero(d, &env->fp_status);
}
@@ -57,7 +57,7 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env)
}
#define CONVERT_BIT(X, SRC, DST) \
- ((SRC) > (DST) \
+ ((unsigned)(SRC) > (unsigned)(DST) \
? (X) / ((SRC) / (DST)) & (DST) \
: ((X) & (SRC)) * ((DST) / (SRC)))
@@ -73,12 +73,12 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
}
set_float_exception_flags(0, &env->fp_status);
- hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, 1u << 0);
- hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, 1u << 1);
- hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, 1u << 2);
- hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, 1u << 3);
- hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, 1u << 4);
- shadow |= hard_exp << (32 - 5);
+ hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, R_FPSR_ENA_I_MASK);
+ hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, R_FPSR_ENA_U_MASK);
+ hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, R_FPSR_ENA_O_MASK);
+ hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, R_FPSR_ENA_Z_MASK);
+ hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, R_FPSR_ENA_V_MASK);
+ shadow |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
env->fr0_shadow = shadow;
env->fr[0] = (uint64_t)shadow << 32;
@@ -378,15 +378,15 @@ static void update_fr0_cmp(CPUHPPAState *env, uint32_t y,
if (y) {
/* targeted comparison */
/* set fpsr[ca[y - 1]] to current compare */
- shadow = deposit32(shadow, 21 - (y - 1), 1, c);
+ shadow = deposit32(shadow, R_FPSR_CA0_SHIFT - (y - 1), 1, c);
} else {
/* queued comparison */
/* shift cq right by one place */
- shadow = deposit32(shadow, 11, 10, extract32(shadow, 12, 10));
+ shadow = (shadow & ~R_FPSR_CQ_MASK) | ((shadow >> 1) & R_FPSR_CQ_MASK);
/* move fpsr[c] to fpsr[cq[0]] */
- shadow = deposit32(shadow, 21, 1, extract32(shadow, 26, 1));
+ shadow = FIELD_DP32(shadow, FPSR, CQ0, FIELD_EX32(shadow, FPSR, C));
/* set fpsr[c] to current compare */
- shadow = deposit32(shadow, 26, 1, c);
+ shadow = FIELD_DP32(shadow, FPSR, C, c);
}
env->fr0_shadow = shadow;
@@ -4322,29 +4322,28 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
switch (a->c) {
case 0: /* simple */
- tcg_gen_andi_i64(t, t, 0x4000000);
- ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0);
- goto done;
+ mask = R_FPSR_C_MASK;
+ break;
case 2: /* rej */
inv = true;
/* fallthru */
case 1: /* acc */
- mask = 0x43ff800;
+ mask = R_FPSR_C_MASK | R_FPSR_CQ_MASK;
break;
case 6: /* rej8 */
inv = true;
/* fallthru */
case 5: /* acc8 */
- mask = 0x43f8000;
+ mask = R_FPSR_C_MASK | R_FPSR_CQ0_6_MASK;
break;
case 9: /* acc6 */
- mask = 0x43e0000;
+ mask = R_FPSR_C_MASK | R_FPSR_CQ0_4_MASK;
break;
case 13: /* acc4 */
- mask = 0x4380000;
+ mask = R_FPSR_C_MASK | R_FPSR_CQ0_2_MASK;
break;
case 17: /* acc2 */
- mask = 0x4200000;
+ mask = R_FPSR_C_MASK | R_FPSR_CQ0_MASK;
break;
default:
gen_illegal(ctx);
@@ -4361,11 +4360,10 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
} else {
unsigned cbit = (a->y ^ 1) - 1;
- tcg_gen_extract_i64(t, t, 21 - cbit, 1);
+ tcg_gen_extract_i64(t, t, R_FPSR_CA0_SHIFT - cbit, 1);
ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0);
}
- done:
return nullify_end(ctx);
}
Define all of the context dependent field definitions. Use FIELD_EX32 and FIELD_DP32 with named fields instead of extract32 and deposit32 with raw constants. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/hppa/cpu.h | 25 +++++++++++++++++++++++++ target/hppa/fpu_helper.c | 26 +++++++++++++------------- target/hppa/translate.c | 18 ++++++++---------- 3 files changed, 46 insertions(+), 23 deletions(-)