From patchwork Tue Apr 16 04:06:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 789204 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:dcf:b0:346:15ad:a2a with SMTP id dw15csp104708wrb; Mon, 15 Apr 2024 21:07:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWpKRyyPEAHswngrbxoDkoSk8FWpMviyUhLV8mi/WSNWVd/gI8VMnrsl12bahAcPxj5eS0rU9LtLAd9PwLg82xd X-Google-Smtp-Source: AGHT+IG+LmCxVTj3XWBk0xLekud6noqpes67MRH8SDUQOxGspf9a2qpnUWvrbMgVkh0dhmScGLPj X-Received: by 2002:a05:622a:1a95:b0:435:15d:8495 with SMTP id s21-20020a05622a1a9500b00435015d8495mr1413224qtc.20.1713240433468; Mon, 15 Apr 2024 21:07:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713240433; cv=none; d=google.com; s=arc-20160816; b=o940KltHjhoOXTMQvv0axvltoVZbP2jYDVY7EroVanKa+6H4HclX/aK1UgvBY+DsLM CqOpcuS7YU10Ltihxp1iJZxBb552tgdj1/AVE7B4nopbyYiOqvRkndEQrhi7Q3sLEYZ7 BzcH1tEVa0LUg1a/jpxTi3laDDVDS89ms/3PV20URdfiY8jnHuMD+f1L75Ns5P1hNkff nUvKVWKcqB4hqMFjaYHuyqzYyeBWpHQwqD/2HrU4pEt++JZZnWlrqdL+QWKaPCJ4jc3V oE+CgP+dXID82wxYzbYygGm64xVzEY5hEH1Grdr185KL4TMfNMOw4HUOj6SLmlIn1Pxn rQvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SGHcSo147SgN6rnFLSb3VGek6gUZYoiow/EIARfgQaI=; fh=HGMLmPLDRBgS2M2DmRioi6Q+pUL3jqoEM8UtJkY6Dtg=; b=NzfsiV8Jv4qTA+LZYrnBIRUAAmSJ1Dqyn85eAz8nuTlmp8CApZnLp8sl4gqXg9plY4 hS8SYrXSNfLOhf0TGvIE1uOSouIp4Qr9UfN9BYF2X+DQMOPA/T482zpZuFuvyuc/zzo7 TBdedXKoofj4v56JX7ecO3whu7WjRf+wgk/c1jKv1W+HhjmpqZN7DDwcvfevQYjGDXgQ xJPzKQCw94Kba9+xdN/pSSm9JYuU0rkteP+S7Ww8RYdGPxtwlQ5jn3n10kbGi5eHqz5y zG1prMuTiT6sizlfMolk9Btb+xnO+pxkX2qBLL6P+QY1tBB2qiwHpW4NEG/2DezZ9pOX Cjvg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qnvBKeqv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a14-20020a05622a064e00b004369300f12fsi9101930qtb.684.2024.04.15.21.07.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Apr 2024 21:07:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qnvBKeqv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rwa5P-0008Ff-As; Tue, 16 Apr 2024 00:06:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rwa5N-0008C0-5E for qemu-devel@nongnu.org; Tue, 16 Apr 2024 00:06:21 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rwa5K-0007Aa-St for qemu-devel@nongnu.org; Tue, 16 Apr 2024 00:06:20 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1e3ff14f249so30376775ad.1 for ; Mon, 15 Apr 2024 21:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1713240377; x=1713845177; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SGHcSo147SgN6rnFLSb3VGek6gUZYoiow/EIARfgQaI=; b=qnvBKeqvUCwKHGbcCgTHflcOR52tZpqyQ3ziHizT+ldJO9Z2Xe72jluHKDGdjStJPX 2lVqogXRpVUiU3Nrl3iVM5AmaS/P7Dl4VKd0GwFBG0xqsDO3Nc/NHy4YPn6GZmYYtPUv ZgUQ8ofPQfp9mFnSzz5huoXWdWzSJUaMVdy5KcKu0PCdpUYDvsL/GggYmkWrQJt9K11y 6Fw7QXaiqWidt6V+HJkx4bg0+rYFk6dm7/rPGNSCwmTJLwH4g1ucFOPezP6NCemyLx19 VtVBQ7iI4TiXU84Z7ng4QblT42b44e0wwkI9DTbjKhuyDbGoa2GFxPhwLyzSWI9+JtY9 v4DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713240377; x=1713845177; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SGHcSo147SgN6rnFLSb3VGek6gUZYoiow/EIARfgQaI=; b=cx9bqepdFcVCV54jYIZnzyIUloNCnf5hbGxXt7F6/AwbxwZKvkwzVUyAfQ/x15usfV tGzFkd0MIYHGmIcuZEFD7JK10a/87HP0INZ7Gziz1dXrG23onB1VxaZWVTlgorx/cJ/W bGyzDBsGJhFfkvexaUmM9P9tWPMY3Kro/g4v8ZOasAinSU1tHefauI5ebThTgLpxQEIi 6d5JEMyHTRZDgaQylw9XDViwqgXEy1i7F8bSoZRuC67CAIjhzEBT5GCnQbU7XK8tp8iW Gcv8WBgNsWXViUzvMSwOzWRbFx0NbI3F/U1sm3XI1BoAN50CRWk04j/XREIwQzVXSwxH V78A== X-Gm-Message-State: AOJu0YzYPeMDB1MdfmF6tAM1g0qbLgsdDBZF8fRY6cp1ZkZU6+t+EyEq cDqJnsGHHP7IxIlBfMqVDwYi0MgDj0I4dsewgpJSUPg/ICYPDRhVPeSw62PpzWjEk9xqzaDNM36 n X-Received: by 2002:a17:903:41c7:b0:1e3:ce12:ef77 with SMTP id u7-20020a17090341c700b001e3ce12ef77mr1256616ple.11.1713240377293; Mon, 15 Apr 2024 21:06:17 -0700 (PDT) Received: from stoup.. (174-21-72-5.tukw.qwest.net. [174.21.72.5]) by smtp.gmail.com with ESMTPSA id l1-20020a170902f68100b001e3e244e5c0sm8694439plg.78.2024.04.15.21.06.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 21:06:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org Subject: [PATCH 7/7] target/i386: Implement TCGCPUOps for plugin register reads Date: Mon, 15 Apr 2024 21:06:09 -0700 Message-Id: <20240416040609.1313605-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240416040609.1313605-1-richard.henderson@linaro.org> References: <20240416040609.1313605-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/i386/tcg/tcg-cpu.c | 72 ++++++++++++++++++++++++++++++--------- 1 file changed, 56 insertions(+), 16 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index cca19cd40e..2370053df2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -22,9 +22,11 @@ #include "helper-tcg.h" #include "qemu/accel.h" #include "hw/core/accel-cpu.h" - +#include "gdbstub/helpers.h" +#include "gdb-internal.h" #include "tcg-cpu.h" + /* Frob eflags into and out of the CPU temporary format. */ static void x86_cpu_exec_enter(CPUState *cs) @@ -61,38 +63,74 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, } } -static void x86_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) +static uint64_t eip_from_unwind(CPUX86State *env, const TranslationBlock *tb, + uint64_t data0) { - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - int cc_op = data[1]; uint64_t new_pc; if (tb_cflags(tb) & CF_PCREL) { /* - * data[0] in PC-relative TBs is also a linear address, i.e. an address with - * the CS base added, because it is not guaranteed that EIP bits 12 and higher - * stay the same across the translation block. Add the CS base back before - * replacing the low bits, and subtract it below just like for !CF_PCREL. + * data[0] in PC-relative TBs is also a linear address, + * i.e. an address with the CS base added, because it is + * not guaranteed that EIP bits 12 and higher stay the + * same across the translation block. Add the CS base + * back before replacing the low bits, and subtract it + * below just like for !CF_PCREL. */ uint64_t pc = env->eip + tb->cs_base; - new_pc = (pc & TARGET_PAGE_MASK) | data[0]; + new_pc = (pc & TARGET_PAGE_MASK) | data0; } else { - new_pc = data[0]; + new_pc = data0; } if (tb->flags & HF_CS64_MASK) { - env->eip = new_pc; - } else { - env->eip = (uint32_t)(new_pc - tb->cs_base); + return new_pc; } + return (uint32_t)(new_pc - tb->cs_base); +} +static void x86_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + CPUX86State *env = cpu_env(cs); + CCOp cc_op; + + env->eip = eip_from_unwind(env, tb, data[0]); + + cc_op = data[1]; if (cc_op != CC_OP_DYNAMIC) { env->cc_op = cc_op; } } +static bool x86_plugin_need_unwind_for_reg(CPUState *cs, int reg) +{ + return reg == IDX_IP_REG || reg == IDX_FLAGS_REG; +} + +static int x86_plugin_unwind_read_reg(CPUState *cs, GByteArray *buf, int reg, + const TranslationBlock *tb, + const uint64_t *data) +{ + CPUX86State *env = cpu_env(cs); + CCOp cc_op; + + switch (reg) { + case IDX_IP_REG: + return gdb_get_regl(buf, eip_from_unwind(env, tb, data[0])); + + case IDX_FLAGS_REG: + cc_op = data[1]; + if (cc_op == CC_OP_DYNAMIC) { + cc_op = env->cc_op; + } + return gdb_get_reg32(buf, cpu_compute_eflags_ccop(env, cc_op)); + + default: + g_assert_not_reached(); + } +} + #ifndef CONFIG_USER_ONLY static bool x86_debug_check_breakpoint(CPUState *cs) { @@ -110,6 +148,8 @@ static const TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .restore_state_to_opc = x86_restore_state_to_opc, + .plugin_need_unwind_for_reg = x86_plugin_need_unwind_for_reg, + .plugin_unwind_read_reg = x86_plugin_unwind_read_reg, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, #ifdef CONFIG_USER_ONLY