From patchwork Fri Mar 29 22:31:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784094 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429042wrt; Fri, 29 Mar 2024 15:32:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVb+dc3mUejCpW7Pqlt1Pl2AK6M8dgaNNvPaiqydXSzZI7P+m8c77g+tHC+XfGaPuF4rf4Fwox9M2o4Mm1ahENQ X-Google-Smtp-Source: AGHT+IHgSDICJIV+whsGHJVclbt09EzsY5YZZndKIZku8jdH18tlPzGi0c9PTjijy4eUOCPet7Nb X-Received: by 2002:ac8:5c8d:0:b0:431:172d:645d with SMTP id r13-20020ac85c8d000000b00431172d645dmr11497957qta.26.1711751557152; Fri, 29 Mar 2024 15:32:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751557; cv=none; d=google.com; s=arc-20160816; b=jvOIO7v0ddI0ylW1GoSrkg7nBzo7MVnbW4XsNVQw5gztnSdsYR3V+ZYwn/GYL0JeBj WrIcBQjyrvTZVzXWDRThOVFfP4rVBB6eDiuko4sB9U1cR3u+eEydTyo6KFYsL75x8/Vp 9aX6FyU58JXwtz26zMdLcgyeqUt4SnDhnq8wAq2vsQcFb0DEJNz0W8UqtX4f7NzS5SXF fv60aNFP10349BgvPFRLMUUGoHRy0qdgkFDNFdQ7PXSAQzS5HLEWumVgLBieT+U+1iJK XtdH8fHolToCPt0d4klVSSrpChh1PpHC7pP2x+HeMNuAgE6aRFVShki54/5Ssz+JkxN8 I7Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KMxM9BbQqKkbLwVKQwHtbDKmzoAaG7uKsKCnvfYND6Q=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=wtV5GWmMu1aQAq5prwKPFfEv0YAlMh85Ep2q05AAz/7OWn4AKutJUJ2jBBmNvpZVVi hdOnfEKjJJpELFDvzK2uxiR3USD9Cj+qVU3IPwgeCSTzfQGwilU4LlFbgMzWK38B7Kum 0Wg5vQAOtbjWxt58B170CFcWdz+iEjvR9A/sognAuvotrM83pdrQsv3j7Lpxo1vRLnwV P/EyykbRVDWkXACvw8BFR9i/jjziAIedtC/G+aVIKa6LHm7rootV0lw2nqx9V7hvz/9N S/a94QQEFRU1MHVDdTIP0HjsCzH6D2NLZyyJpo1aTwKrQN4o74kmfnSCjGoH/J6Wms6a njyA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="J/oSCaGf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x9-20020a05622a000900b004315af40767si4622436qtw.666.2024.03.29.15.32.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 29 Mar 2024 15:32:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="J/oSCaGf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rqKl7-0002Zy-Vn; Fri, 29 Mar 2024 18:31:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rqKl4-0002YU-BS for qemu-devel@nongnu.org; Fri, 29 Mar 2024 18:31:36 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rqKl2-0003Wz-De for qemu-devel@nongnu.org; Fri, 29 Mar 2024 18:31:33 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1def89f0cfdso26332425ad.0 for ; Fri, 29 Mar 2024 15:31:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711751491; x=1712356291; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KMxM9BbQqKkbLwVKQwHtbDKmzoAaG7uKsKCnvfYND6Q=; b=J/oSCaGfW2OYnQUJcirGJ1b4ue8Bih9nmdnjRKzAK724ru8KDKkzs+IYrHHBFu70IM uhTRd1G8AZGRyLaInYAuz8t3fV+axxfZ9p4XaeqT4tx5IVH6+/1ekxa1nH8UHBLJ5KC+ 7z+XnXmZP13AHzPbhYMZTpV8Gf600maHwltVKfTnXkppzKnso4ZWSZb/yB8gl8+xip0M yeoS06YMR/64kLwGAz+nJPwvUwJONKpvXzp70e1be0eF5ZL5EC5EP3M75/o2zLjYi8HI THHsjSl5/XYpm61v73FOyXY7jvLim1edcNXsplY5CUC+NPb0oUEbnAXuGwksXDrqpV9t zsxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711751491; x=1712356291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KMxM9BbQqKkbLwVKQwHtbDKmzoAaG7uKsKCnvfYND6Q=; b=lQytqXXMZnT9RVbdTkfkh5yYx+p+NHb1ReVLcXSdcOCeW6J81jcpZHULSekVSZXnjp RCq/z3bmrJdASR6Vuu2JwIu6cr+BcdAD20qZYGtHnOctISr8ZtAEvJeYvx5Cy5lr1Fhh FRuLd/5DOeKAlqoE7qDaQnogbZVHoK496oXgDgKLRWvb/DbJCIbn8soRCWIf/T/ZXJtL X5XWWXdd1k6i+dQ1G6kxhXBnTfjq0cAbV4trQAGeOYFnYmfSpLVYcn7b9DA3O7FsnZFv wj+JE/Edkd45Laav1/qaB5EGTyiJpLlg++jRm+3X7gOF+jtsyGonyKfOnTmSS6ZQMs6I OqCw== X-Gm-Message-State: AOJu0YyaWMOOrmkpPKEBWfId9GpfUyXkpKHtORV1oNG8+QRI1ziXNu8a ETY2cJRPLVaKNOHrUS3ZajnLEQMm6zhl4/sBcXYaGsbqMr7mrPOYBl/qdNAj2GvCVw2rWkKE9bf e X-Received: by 2002:a17:902:e5d0:b0:1e0:c88f:654f with SMTP id u16-20020a170902e5d000b001e0c88f654fmr9713486plf.33.1711751490945; Fri, 29 Mar 2024 15:31:30 -0700 (PDT) Received: from stoup.. (098-147-007-212.res.spectrum.com. [98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 12/18] target/hppa: Squash d for pa1.x during decode Date: Fri, 29 Mar 2024 12:31:05 -1000 Message-Id: <20240329223111.1735826-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The cond_need_ext predicate was created while we still had a 32-bit compilation mode. It now makes more sense to treat D as an absolute indicator of a 64-bit operation. Tested-by: Helge Deller Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 20 +++++++++++++------- target/hppa/translate.c | 38 ++++++++++++++++++++------------------ 2 files changed, 33 insertions(+), 25 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f58455dfdb..6a74cf23cd 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -57,6 +57,9 @@ %neg_to_m 0:1 !function=neg_to_m %a_to_m 2:1 !function=neg_to_m %cmpbid_c 13:2 !function=cmpbid_c +%d_5 5:1 !function=pa20_d +%d_11 11:1 !function=pa20_d +%d_13 13:1 !function=pa20_d #### # Argument set definitions @@ -84,15 +87,16 @@ # Format definitions #### -@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d +@rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=%d_5 @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf -@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=%d_5 @rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh -@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh -@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 +@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d=%d_5 +@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d=%d_5 sh=0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 -@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 +@rri_cf_d ...... r:5 t:5 cf:4 . ........... \ + &rri_cf_d d=%d_11 i=%lowsign_11 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=%assemble_12 @@ -368,8 +372,10 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd # Conditional Branches #### -bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 -bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 +bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \ + disp=%assemble_12 d=%d_13 +bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \ + disp=%assemble_12 d=%d_13 movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 99c5c4cbca..a70d644c0b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -200,6 +200,14 @@ static int cmpbid_c(DisasContext *ctx, int val) return val ? val : 4; /* 0 == "*<<" */ } +/* + * In many places pa1.x did not decode the bit that later became + * the pa2.0 D bit. Suppress D unless the cpu is pa2.0. + */ +static int pa20_d(DisasContext *ctx, int val) +{ + return ctx->is_pa20 & val; +} /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -693,12 +701,6 @@ static bool cond_need_cb(int c) return c == 4 || c == 5; } -/* Need extensions from TCGv_i32 to TCGv_i64. */ -static bool cond_need_ext(DisasContext *ctx, bool d) -{ - return !(ctx->is_pa20 && d); -} - /* * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of * the Parisc 1.1 Architecture Reference Manual for details. @@ -715,7 +717,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, cond = cond_make_f(); break; case 1: /* = / <> (Z / !Z) */ - if (cond_need_ext(ctx, d)) { + if (!d) { tmp = tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, res); res = tmp; @@ -725,7 +727,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_ext32s_i64(tmp, tmp); } cond = cond_make_0_tmp(TCG_COND_LT, tmp); @@ -742,7 +744,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, */ tmp = tcg_temp_new_i64(); tcg_gen_eqv_i64(tmp, res, sv); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_sextract_i64(tmp, tmp, 31, 1); tcg_gen_and_i64(tmp, tmp, res); tcg_gen_ext32u_i64(tmp, tmp); @@ -760,13 +762,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tmp = tcg_temp_new_i64(); tcg_gen_neg_i64(tmp, cb_msb); tcg_gen_and_i64(tmp, tmp, res); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } cond = cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ - if (cond_need_ext(ctx, d)) { + if (!d) { tmp = tcg_temp_new_i64(); tcg_gen_ext32s_i64(tmp, sv); sv = tmp; @@ -827,7 +829,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, if (cf & 1) { tc = tcg_invert_cond(tc); } - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); @@ -904,7 +906,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, g_assert_not_reached(); } - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 tmp = tcg_temp_new_i64(); if (ext_uns) { @@ -979,7 +981,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) static TCGv_i64 get_carry(DisasContext *ctx, bool d, TCGv_i64 cb, TCGv_i64 cb_msb) { - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_extract_i64(t, cb, 32, 1); return t; @@ -3448,12 +3450,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) tmp = tcg_temp_new_i64(); tcg_r = load_gpr(ctx, a->r); - if (cond_need_ext(ctx, a->d)) { + if (a->d) { + tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); + } else { /* Force shift into [32,63] */ tcg_gen_ori_i64(tmp, cpu_sar, 32); tcg_gen_shl_i64(tmp, tcg_r, tmp); - } else { - tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); } cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -3470,7 +3472,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) tmp = tcg_temp_new_i64(); tcg_r = load_gpr(ctx, a->r); - p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); + p = a->p | (a->d ? 0 : 32); tcg_gen_shli_i64(tmp, tcg_r, p); cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);