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[176.184.5.52]) by smtp.gmail.com with ESMTPSA id dr3-20020a170907720300b00a4a38d10801sm896023ejc.35.2024.03.28.08.56.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 28 Mar 2024 08:56:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Eduardo Habkost , Stefano Stabellini , xen-devel@lists.xenproject.org, Bernhard Beschow , Thomas Huth , Marcel Apfelbaum , "Michael S. Tsirkin" , Paolo Bonzini , Igor Mammedov , Anthony Perard , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH-for-9.1 19/29] hw/i386/pc: Pass PcPciMachineState argument to CXL helpers Date: Thu, 28 Mar 2024 16:54:27 +0100 Message-ID: <20240328155439.58719-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240328155439.58719-1-philmd@linaro.org> References: <20240328155439.58719-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since CXL helpers expect a PCI-based machine, we can directly pass them a PcPciMachineState argument. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e36d76656b..d8e91d18b8 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -705,14 +705,14 @@ static void pc_get_device_memory_range(PCMachineState *pcms, *device_mem_size = size; } -static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) +static uint64_t pc_get_cxl_range_start(PcPciMachineState *ppms) { + PCMachineState *pcms = PC_MACHINE(ppms); MachineState *ms = MACHINE(pcms); hwaddr cxl_base; ram_addr_t size; - if (has_reserved_memory(pcms) && - (ms->ram_size < ms->maxram_size)) { + if ((ms->ram_size < ms->maxram_size)) { pc_get_device_memory_range(pcms, &cxl_base, &size); cxl_base += size; } else { @@ -722,10 +722,9 @@ static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) return cxl_base; } -static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) +static uint64_t pc_get_cxl_range_end(PcPciMachineState *ppms) { - PcPciMachineState *ppms = PC_PCI_MACHINE(pcms); - uint64_t start = pc_get_cxl_range_start(pcms) + MiB; + uint64_t start = pc_get_cxl_range_start(ppms) + MiB; if (ppms->cxl_devices_state.fixed_windows) { GList *it; @@ -937,7 +936,7 @@ void pc_memory_init(PCMachineState *pcms, MemoryRegion *mr = &ppms->cxl_devices_state.host_mr; hwaddr cxl_size = MiB; - cxl_base = pc_get_cxl_range_start(pcms); + cxl_base = pc_get_cxl_range_start(ppms); memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); memory_region_add_subregion(system_memory, cxl_base, mr); cxl_resv_end = cxl_base + cxl_size; @@ -1027,7 +1026,7 @@ uint64_t pc_pci_hole64_start(void) ram_addr_t size = 0; if (ppms->cxl_devices_state.is_enabled) { - hole64_start = pc_get_cxl_range_end(pcms); + hole64_start = pc_get_cxl_range_end(ppms); } else if (has_reserved_memory(pcms) && (ms->ram_size < ms->maxram_size)) { pc_get_device_memory_range(pcms, &hole64_start, &size); if (!pcmc->broken_reserved_end) {