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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id n15-20020a170902d2cf00b001dcfaab3457sm1811758plc.104.2024.03.23.10.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Mar 2024 10:30:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: svens@stackframe.org, deller@gmx.de Subject: [PATCH v2 4/7] target/hppa: Fix ADD/SUB trap on overflow for narrow mode Date: Sat, 23 Mar 2024 07:29:51 -1000 Message-Id: <20240323172954.1041480-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240323172954.1041480-1-richard.henderson@linaro.org> References: <20240323172954.1041480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Sven Schnelle Fixes: c53e401ed9ff ("target/hppa: Remove TARGET_REGISTER_BITS") Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Message-Id: <20240321184228.611897-2-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2cb91956da..ceb739c54a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1126,6 +1126,9 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_add_sv(ctx, dest, in1, in2); if (is_tsv) { + if (!d) { + tcg_gen_ext32s_i64(sv, sv); + } /* ??? Need to include overflow from shift. */ gen_helper_tsv(tcg_env, sv); } @@ -1217,6 +1220,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { + if (!d) { + tcg_gen_ext32s_i64(sv, sv); + } gen_helper_tsv(tcg_env, sv); } }