@@ -47,6 +47,8 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
+DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
+DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
DEF_HELPER_2(raise_exception, noreturn, env, int)
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
@@ -458,6 +458,52 @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
return finish_fcmp(env, r, GETPC());
}
+uint32_t helper_flcmps(float32 src1, float32 src2)
+{
+ /*
+ * FLCMP never raises an exception nor modifies any FSR fields.
+ * Perform the comparison with a dummy fp environment.
+ */
+ float_status discard = { };
+ FloatRelation r = float32_compare_quiet(src1, src2, &discard);
+
+ switch (r) {
+ case float_relation_equal:
+ if (src2 == float32_zero && src1 != float32_zero) {
+ return 1; /* -0.0 < +0.0 */
+ }
+ return 0;
+ case float_relation_less:
+ return 1;
+ case float_relation_greater:
+ return 0;
+ case float_relation_unordered:
+ return float32_is_any_nan(src2) ? 3 : 2;
+ }
+ g_assert_not_reached();
+}
+
+uint32_t helper_flcmpd(float64 src1, float64 src2)
+{
+ float_status discard = { };
+ FloatRelation r = float64_compare_quiet(src1, src2, &discard);
+
+ switch (r) {
+ case float_relation_equal:
+ if (src2 == float64_zero && src1 != float64_zero) {
+ return 1; /* -0.0 < +0.0 */
+ }
+ return 0;
+ case float_relation_less:
+ return 1;
+ case float_relation_greater:
+ return 0;
+ case float_relation_unordered:
+ return float64_is_any_nan(src2) ? 3 : 2;
+ }
+ g_assert_not_reached();
+}
+
target_ulong cpu_get_fsr(CPUSPARCState *env)
{
target_ulong fsr = env->fsr | env->fsr_cexc_ftt;
@@ -5199,6 +5199,40 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e)
TRANS(FCMPq, ALL, do_fcmpq, a, false)
TRANS(FCMPEq, ALL, do_fcmpq, a, true)
+static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
+{
+ TCGv_i32 src1, src2;
+
+ if (!avail_VIS3(dc)) {
+ return false;
+ }
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ src1 = gen_load_fpr_F(dc, a->rs1);
+ src2 = gen_load_fpr_F(dc, a->rs2);
+ gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
+ return advance_pc(dc);
+}
+
+static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
+{
+ TCGv_i64 src1, src2;
+
+ if (!avail_VIS3(dc)) {
+ return false;
+ }
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ src1 = gen_load_fpr_D(dc, a->rs1);
+ src2 = gen_load_fpr_D(dc, a->rs2);
+ gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
+ return advance_pc(dc);
+}
+
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
@@ -470,6 +470,10 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
FZEROs 10 rd:5 110110 00000 0 0110 0001 00000
FONEd 10 ..... 110110 00000 0 0111 1110 00000 rd=%dfp_rd
FONEs 10 rd:5 110110 00000 0 0111 1111 00000
+
+ FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5
+ FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \
+ rs1=%dfp_rs1 rs2=%dfp_rs2
]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
}
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/helper.h | 2 ++ target/sparc/fop_helper.c | 46 +++++++++++++++++++++++++++++++++++++++ target/sparc/translate.c | 34 +++++++++++++++++++++++++++++ target/sparc/insns.decode | 4 ++++ 4 files changed, 86 insertions(+)