From patchwork Tue Feb 27 13:32:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 776222 Delivered-To: patch@linaro.org Received: by 2002:adf:a113:0:b0:33d:f458:43ce with SMTP id o19csp159941wro; Tue, 27 Feb 2024 05:44:13 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVoxJ0uqo4+RDtU4dRBurWpDZDMILBkgxYeY4TLhWOiIZH2UqwhpUs+JtHxMaKqScxsPO81sZRINhCKo9a8kztg X-Google-Smtp-Source: AGHT+IExuUqSynnQ6mLqZHuXscIfsD5nEa+5Pmvoy1CX5WnJAM8n6MeLozBNaxzK3FUlMkKIk4Cs X-Received: by 2002:a67:ead7:0:b0:471:c4ad:4119 with SMTP id s23-20020a67ead7000000b00471c4ad4119mr6386312vso.8.1709041453647; Tue, 27 Feb 2024 05:44:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1709041453; cv=none; d=google.com; s=arc-20160816; b=jxt8upPx8fczH4HOlLA1dJlXH16URpZFJmrMMqTw3yT+f9FNiubH243/Xn6cfXGFyl CPeheCtwm2wdwaoLDrOO/3C8Haky+UktES5bwf0csTU3S2NGeKuq7up+L8CwJUmuXmoi xNEqqnTsuvIZSbtwm5txJ2JliyrhgSrpiDEDFKTxn8h9Eotb0b8RqqG7GJXtllEcJylb hJ9Yx9Vpo89sDzdgM+dWEAcD/6HDJR6MHfy+Phvdc5ohqmmHAknwGX3GS4rIGD0HHOoH ZCMr9x1F1gGFI07a07lpGe0W9DLoUvJ+s8OlFBC70E0mIvrjOHd28P2WRy0QjlvgIzVn d8Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bnsDuxpc/9b0o5hbfDhwh9os93CNP+sIRCB+KuakBY0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=YTrj2EwzD0FiWZxm/CS62CnSG3bzk2ZYW3mIjGDLSUcmuMVnonXd4nx2DZv4AFw2Z8 bU1c7f/qWLS9efNasSSyZEocZpqOUsK1n+DCECBZn3PfgOxBIGVP09W0bXNpm5jM5hl8 AxZlK+JIpXVh1iZMiA/LJ+80oTFbY8px1ot4qIe5zvoTZnBH9vrfVbgoWuklk4QCIKoq gRcjaov6GbztBLZnldSLtAmWC+sLoaOYhi1+5ZRQMxcp2s7w8vT0365qSHwP3SkTdOyl Rrq7Wrx6tbpFeGoXoff7XlT6tObFqu3eTVn4Hku5kBm0HbrbptNEsiiJYDWnlLD9nJI2 7zbA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=btp6LAY+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m15-20020ac8688f000000b0042e6dab52f2si7277067qtq.430.2024.02.27.05.44.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Feb 2024 05:44:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=btp6LAY+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rexam-0000te-Tm; Tue, 27 Feb 2024 08:33:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rexaX-0000oV-Dx for qemu-devel@nongnu.org; Tue, 27 Feb 2024 08:33:41 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rexaQ-0002uS-Ne for qemu-devel@nongnu.org; Tue, 27 Feb 2024 08:33:41 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-33de6da5565so805065f8f.2 for ; Tue, 27 Feb 2024 05:33:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709040811; x=1709645611; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bnsDuxpc/9b0o5hbfDhwh9os93CNP+sIRCB+KuakBY0=; b=btp6LAY+vXYimAmMXIpd4wSnwV0bClwiGWlO1OXj9saGm6MHGS+5GOHEQZgZb/v6ub uoctr1IRzMs0JRTH4j0TDKcBxc6FzgZE8Ix84eqM8PUyi42dVZl6sB7CVr0upfP+J9nm lpV+XBsr3g4gej51SsU3iJ/w/9jx7qNRKvvmAHx2NuD5AZv0eKzE/wDUdu3gt2xE/+qj q1eVVmGMn4hrEYotANX8eQNtRxHbJHSOt3aKcYqqo4FY9OR8zYRA3SG2oQ1l4MzWtFVg J1rtd/PKSNrtP+BSKdMfglTZOCu910rgpbqBqWHAH2brd2p6NJ+Rsk+yYW1+6KTsqb5v 1+QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709040811; x=1709645611; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bnsDuxpc/9b0o5hbfDhwh9os93CNP+sIRCB+KuakBY0=; b=M8HVYBlT8NnlqmpIPluZy4MrlMXFWoPg6haxH1xCAagSY8QpVeiDl9WmXvUcWxvXRZ C88+0cG/lH2g5Cg37MQbl4GJVfuFybQ5rSXbT3VhvMt5nTBqC+ljlb/JTEMXeSmDcUfO V85Y+p3GWluB2YfbNROZAJ6OnqrSmhlmDwhYLrn0MtdIYpD1BQfZHoKti0kiot2UAQSq Tia/2pu6BP0j45N84BMHOJc+QGlEdw9mofWN344ROz3eMmhiNj/5cjcZRXF23ztf3PVw dA8eRJa4HdBoBARKtcWzXH9LxB+XoV1+RZ9TovQxosJ+MZeh14lrGu01VwqtI21u9EMa coFw== X-Gm-Message-State: AOJu0Yz0VjaJFER7YiNvVnAZfQ/UVWkC2553gnq5mWWmAa1WID+kE3HZ HZBD9DwZRbbhnLmQIGog95dLfZUuwVIuzS+o15YHJF1bvtTj3Xor0l9UyMpnFIDzg8G2BrpB6Ob w X-Received: by 2002:adf:f684:0:b0:33d:6bd3:9e24 with SMTP id v4-20020adff684000000b0033d6bd39e24mr7247269wrp.1.1709040810966; Tue, 27 Feb 2024 05:33:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i13-20020adfe48d000000b0033ae7d768b2sm11319552wrm.117.2024.02.27.05.33.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 05:33:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/45] hw/arm: Add GPIO and SD to BCM2838 periph Date: Tue, 27 Feb 2024 13:32:58 +0000 Message-Id: <20240227133314.1721857-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227133314.1721857-1-peter.maydell@linaro.org> References: <20240227133314.1721857-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Sergey Kambalin Signed-off-by: Sergey Kambalin Reviewed-by: Peter Maydell Message-id: 20240226000259.2752893-10-sergey.kambalin@auriga.com Signed-off-by: Peter Maydell --- include/hw/arm/bcm2838_peripherals.h | 8 ++ hw/arm/bcm2838_peripherals.c | 143 +++++++++++++++++++++++++++ 2 files changed, 151 insertions(+) diff --git a/include/hw/arm/bcm2838_peripherals.h b/include/hw/arm/bcm2838_peripherals.h index d07831753ab..86b0d96944e 100644 --- a/include/hw/arm/bcm2838_peripherals.h +++ b/include/hw/arm/bcm2838_peripherals.h @@ -10,6 +10,8 @@ #define BCM2838_PERIPHERALS_H #include "hw/arm/bcm2835_peripherals.h" +#include "hw/sd/sdhci.h" +#include "hw/gpio/bcm2838_gpio.h" /* SPI */ #define GIC_SPI_INTERRUPT_MBOX 33 @@ -45,6 +47,9 @@ #define GPU_INTERRUPT_DMA14 28 #define GPU_INTERRUPT_DMA15 31 +#define BCM2838_MPHI_OFFSET 0xb200 +#define BCM2838_MPHI_SIZE 0x200 + #define TYPE_BCM2838_PERIPHERALS "bcm2838-peripherals" OBJECT_DECLARE_TYPE(BCM2838PeripheralState, BCM2838PeripheralClass, BCM2838_PERIPHERALS) @@ -58,6 +63,9 @@ struct BCM2838PeripheralState { MemoryRegion peri_low_mr_alias; MemoryRegion mphi_mr_alias; + SDHCIState emmc2; + BCM2838GpioState gpio; + OrIRQState mmc_irq_orgate; OrIRQState dma_7_8_irq_orgate; OrIRQState dma_9_10_irq_orgate; diff --git a/hw/arm/bcm2838_peripherals.c b/hw/arm/bcm2838_peripherals.c index 06110c724f8..55ae56733f4 100644 --- a/hw/arm/bcm2838_peripherals.c +++ b/hw/arm/bcm2838_peripherals.c @@ -15,22 +15,56 @@ /* Lower peripheral base address on the VC (GPU) system bus */ #define BCM2838_VC_PERI_LOW_BASE 0x7c000000 +/* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ +#define BCM2835_SDHC_CAPAREG 0x52134b4 + static void bcm2838_peripherals_init(Object *obj) { BCM2838PeripheralState *s = BCM2838_PERIPHERALS(obj); BCM2838PeripheralClass *bc = BCM2838_PERIPHERALS_GET_CLASS(obj); + BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(obj); /* Lower memory region for peripheral devices (exported to the Soc) */ memory_region_init(&s->peri_low_mr, obj, "bcm2838-peripherals", bc->peri_low_size); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_low_mr); + /* Extended Mass Media Controller 2 */ + object_initialize_child(obj, "emmc2", &s->emmc2, TYPE_SYSBUS_SDHCI); + + /* GPIO */ + object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2838_GPIO); + + object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", + OBJECT(&s_base->sdhci.sdbus)); + object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", + OBJECT(&s_base->sdhost.sdbus)); + + object_initialize_child(obj, "mmc_irq_orgate", &s->mmc_irq_orgate, + TYPE_OR_IRQ); + object_property_set_int(OBJECT(&s->mmc_irq_orgate), "num-lines", 2, + &error_abort); + + object_initialize_child(obj, "dma_7_8_irq_orgate", &s->dma_7_8_irq_orgate, + TYPE_OR_IRQ); + object_property_set_int(OBJECT(&s->dma_7_8_irq_orgate), "num-lines", 2, + &error_abort); + + object_initialize_child(obj, "dma_9_10_irq_orgate", &s->dma_9_10_irq_orgate, + TYPE_OR_IRQ); + object_property_set_int(OBJECT(&s->dma_9_10_irq_orgate), "num-lines", 2, + &error_abort); } static void bcm2838_peripherals_realize(DeviceState *dev, Error **errp) { + DeviceState *mmc_irq_orgate; + DeviceState *dma_7_8_irq_orgate; + DeviceState *dma_9_10_irq_orgate; + MemoryRegion *mphi_mr; BCM2838PeripheralState *s = BCM2838_PERIPHERALS(dev); BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(dev); + int n; bcm_soc_peripherals_common_realize(dev, errp); @@ -42,6 +76,115 @@ static void bcm2838_peripherals_realize(DeviceState *dev, Error **errp) BCM2838_VC_PERI_LOW_BASE, &s->peri_low_mr_alias, 1); + /* Extended Mass Media Controller 2 */ + object_property_set_uint(OBJECT(&s->emmc2), "sd-spec-version", 3, + &error_abort); + object_property_set_uint(OBJECT(&s->emmc2), "capareg", + BCM2835_SDHC_CAPAREG, &error_abort); + object_property_set_bool(OBJECT(&s->emmc2), "pending-insert-quirk", true, + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc2), errp)) { + return; + } + + memory_region_add_subregion(&s_base->peri_mr, EMMC2_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->emmc2), + 0)); + + /* According to DTS, EMMC and EMMC2 share one irq */ + if (!qdev_realize(DEVICE(&s->mmc_irq_orgate), NULL, errp)) { + return; + } + + mmc_irq_orgate = DEVICE(&s->mmc_irq_orgate); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc2), 0, + qdev_get_gpio_in(mmc_irq_orgate, 0)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->sdhci), 0, + qdev_get_gpio_in(mmc_irq_orgate, 1)); + + /* Connect EMMC and EMMC2 to the interrupt controller */ + qdev_connect_gpio_out(mmc_irq_orgate, 0, + qdev_get_gpio_in_named(DEVICE(&s_base->ic), + BCM2835_IC_GPU_IRQ, + INTERRUPT_ARASANSDIO)); + + /* Connect DMA 0-6 to the interrupt controller */ + for (n = 0; n < 7; n++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n, + qdev_get_gpio_in_named(DEVICE(&s_base->ic), + BCM2835_IC_GPU_IRQ, + GPU_INTERRUPT_DMA0 + n)); + } + + /* According to DTS, DMA 7 and 8 share one irq */ + if (!qdev_realize(DEVICE(&s->dma_7_8_irq_orgate), NULL, errp)) { + return; + } + dma_7_8_irq_orgate = DEVICE(&s->dma_7_8_irq_orgate); + + /* Connect DMA 7-8 to the interrupt controller */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 7, + qdev_get_gpio_in(dma_7_8_irq_orgate, 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 8, + qdev_get_gpio_in(dma_7_8_irq_orgate, 1)); + + qdev_connect_gpio_out(dma_7_8_irq_orgate, 0, + qdev_get_gpio_in_named(DEVICE(&s_base->ic), + BCM2835_IC_GPU_IRQ, + GPU_INTERRUPT_DMA7_8)); + + /* According to DTS, DMA 9 and 10 share one irq */ + if (!qdev_realize(DEVICE(&s->dma_9_10_irq_orgate), NULL, errp)) { + return; + } + dma_9_10_irq_orgate = DEVICE(&s->dma_9_10_irq_orgate); + + /* Connect DMA 9-10 to the interrupt controller */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 9, + qdev_get_gpio_in(dma_9_10_irq_orgate, 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 10, + qdev_get_gpio_in(dma_9_10_irq_orgate, 1)); + + qdev_connect_gpio_out(dma_9_10_irq_orgate, 0, + qdev_get_gpio_in_named(DEVICE(&s_base->ic), + BCM2835_IC_GPU_IRQ, + GPU_INTERRUPT_DMA9_10)); + + /* Connect DMA 11-14 to the interrupt controller */ + for (n = 11; n < 15; n++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n, + qdev_get_gpio_in_named(DEVICE(&s_base->ic), + BCM2835_IC_GPU_IRQ, + GPU_INTERRUPT_DMA11 + n + - 11)); + } + + /* + * Connect DMA 15 to the interrupt controller, it is physically removed + * from other DMA channels and exclusively used by the GPU + */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 15, + qdev_get_gpio_in_named(DEVICE(&s_base->ic), + BCM2835_IC_GPU_IRQ, + GPU_INTERRUPT_DMA15)); + + /* Map MPHI to BCM2838 memory map */ + mphi_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s_base->mphi), 0); + memory_region_init_alias(&s->mphi_mr_alias, OBJECT(s), "mphi", mphi_mr, 0, + BCM2838_MPHI_SIZE); + memory_region_add_subregion(&s_base->peri_mr, BCM2838_MPHI_OFFSET, + &s->mphi_mr_alias); + + /* GPIO */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { + return; + } + memory_region_add_subregion( + &s_base->peri_mr, GPIO_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0)); + + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus"); } static void bcm2838_peripherals_class_init(ObjectClass *oc, void *data)