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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id cc3-20020a5d5c03000000b0033d5e3c6835sm5702004wrb.5.2024.02.20.11.26.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 11:26:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= , Mark Cave-Ayland , Bernhard Beschow , Richard Henderson , Markus Armbruster , Alexander Graf , Anton Johansson , Paolo Bonzini , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 1/2] target/alpha: Expose TMR and SMP IRQ lines via QDev Date: Tue, 20 Feb 2024 20:26:24 +0100 Message-ID: <20240220192625.17944-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220192625.17944-1-philmd@linaro.org> References: <20240220192625.17944-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to remove calls to cpu_interrupt() from hw/ code, expose the TMR and SMP interrupts via QDev as named GPIOs. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index bf70173a25..619cd54593 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,31 @@ #include "cpu.h" #include "exec/exec-all.h" +#ifndef CONFIG_USER_ONLY +static void alpha_cpu_tmr_irq(void *opaque, int irq, int level) +{ + DeviceState *dev = opaque; + CPUState *cs = CPU(dev); + + if (level) { + cs->interrupt_request |= CPU_INTERRUPT_TIMER; + } else { + cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; + } +} + +static void alpha_cpu_smp_irq(void *opaque, int irq, int level) +{ + DeviceState *dev = opaque; + CPUState *cs = CPU(dev); + + if (level) { + cs->interrupt_request |= CPU_INTERRUPT_SMP; + } else { + cs->interrupt_request &= ~CPU_INTERRUPT_SMP; + } +} +#endif static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { @@ -89,6 +114,11 @@ static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); +#ifndef CONFIG_USER_ONLY + qdev_init_gpio_in_named(dev, alpha_cpu_tmr_irq, "TMR", 1); + qdev_init_gpio_in_named(dev, alpha_cpu_smp_irq, "SMP", 1); +#endif + acc->parent_realize(dev, errp); }