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Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 03/14] hw/acpi/ich9: Restrict definitions from 'hw/southbridge/ich9.h' Date: Mon, 19 Feb 2024 17:38:43 +0100 Message-ID: <20240219163855.87326-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Restrict ACPI definitions from "hw/southbridge/ich9.h" to the ACPI files where they are used. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/acpi/ich9.h | 15 +++++++++++++++ include/hw/southbridge/ich9.h | 18 ------------------ hw/acpi/ich9.c | 4 ++++ 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 215de3c91f..3587a35c9f 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -91,4 +91,19 @@ void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, bool ich9_pm_is_hotpluggable_bus(HotplugHandler *hotplug_dev, BusState *bus); void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list); + +#define ICH9_PMIO_PM1_STS 0x00 +#define ICH9_PMIO_PM1_EN 0x02 +#define ICH9_PMIO_PM1_CNT 0x04 +#define ICH9_PMIO_PM1_TMR 0x08 +#define ICH9_PMIO_GPE0_STS 0x20 +#define ICH9_PMIO_GPE0_EN 0x28 +#define ICH9_PMIO_GPE0_LEN 16 +#define ICH9_PMIO_SMI_EN 0x30 +#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) +#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) +#define ICH9_PMIO_SMI_STS 0x34 +#define ICH9_PMIO_TCO_RLD 0x60 +#define ICH9_PMIO_TCO_LEN 32 + #endif /* HW_ACPI_ICH9_H */ diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index fd01649d04..1ac4238f7e 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -183,24 +183,6 @@ struct ICH9LPCState { /* D31:F0 power management I/O registers offset from the address ICH9_LPC_PMBASE */ -/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ -#define ICH9_PMIO_SIZE 128 -#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) - -#define ICH9_PMIO_PM1_STS 0x00 -#define ICH9_PMIO_PM1_EN 0x02 -#define ICH9_PMIO_PM1_CNT 0x04 -#define ICH9_PMIO_PM1_TMR 0x08 -#define ICH9_PMIO_GPE0_STS 0x20 -#define ICH9_PMIO_GPE0_EN 0x28 -#define ICH9_PMIO_GPE0_LEN 16 -#define ICH9_PMIO_SMI_EN 0x30 -#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) -#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) -#define ICH9_PMIO_SMI_STS 0x34 -#define ICH9_PMIO_TCO_RLD 0x60 -#define ICH9_PMIO_TCO_LEN 32 - /* FADT ACPI_ENABLE/ACPI_DISABLE */ #define ICH9_APM_ACPI_ENABLE 0x2 #define ICH9_APM_ACPI_DISABLE 0x3 diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index be375a8b9d..228ebc9a1e 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -49,6 +49,10 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) #define ICH9_DEBUG(fmt, ...) do { } while (0) #endif +/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ +#define ICH9_PMIO_SIZE 128 +#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) + static void ich9_pm_update_sci_fn(ACPIREGS *regs) { ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);