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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q16-20020adfea10000000b0033cfa00e497sm2384129wrm.64.2024.02.15.09.35.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 09:35:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register Date: Thu, 15 Feb 2024 17:35:30 +0000 Message-Id: <20240215173538.2430599-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215173538.2430599-1-peter.maydell@linaro.org> References: <20240215173538.2430599-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We currently guard the CFG3 register read with (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) which is clearly wrong as it is never true. This register is present on all board types except AN524 and AN527; correct the condition. Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547") Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240206132931.38376-6-peter.maydell@linaro.org --- hw/misc/mps2-scc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 6cfb5ff1086..6c1b1cd3795 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -118,7 +118,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) r = s->cfg2; break; case A_CFG3: - if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) { + if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) { /* CFG3 reserved on AN524 */ goto bad_offset; }