| Message ID | 20240206132931.38376-3-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | hw/arm: Implement new machine mps3-an536 (Cortex-R52 MPS3 AN536 FPGA image) | expand |
On 2/6/24 23:29, Peter Maydell wrote: > The Cortex-R52 implements the Configuration Base Address Register > (CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU > type, so that our implementation provides the register and the > associated qdev property. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/tcg/cpu32.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c > index 11253051156..311d654cdce 100644 > --- a/target/arm/tcg/cpu32.c > +++ b/target/arm/tcg/cpu32.c > @@ -809,6 +809,7 @@ static void cortex_r52_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_PMSA); > set_feature(&cpu->env, ARM_FEATURE_NEON); > set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); > + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); Reviewed-by: Richard Henderson <richard.henderson@linaro.org> I just noticed that arm_cpu_post_init can be simplified to not check CBAR_RO, now that we have arm_cpu_propagate_feature_implications. r~
On Tue, 6 Feb 2024 at 20:38, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 2/6/24 23:29, Peter Maydell wrote: > > The Cortex-R52 implements the Configuration Base Address Register > > (CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU > > type, so that our implementation provides the register and the > > associated qdev property. > > > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > > --- > > target/arm/tcg/cpu32.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c > > index 11253051156..311d654cdce 100644 > > --- a/target/arm/tcg/cpu32.c > > +++ b/target/arm/tcg/cpu32.c > > @@ -809,6 +809,7 @@ static void cortex_r52_initfn(Object *obj) > > set_feature(&cpu->env, ARM_FEATURE_PMSA); > > set_feature(&cpu->env, ARM_FEATURE_NEON); > > set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); > > + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > I just noticed that arm_cpu_post_init can be simplified to not check CBAR_RO, now that we > have arm_cpu_propagate_feature_implications. The other bit of CBAR cleanup I have is that cortex-a55, cortex-a76, neoverse-n1, neoverse-v1, neoverse-v2 and cortex-a710 have all cut-n-pasted the line that sets ARM_FEATURE_CBAR_RO, but none of them actually have a CBAR according to their TRM. The only reason I didn't throw in a patch fixing that is that I think it would be a migration compat break and I didn't feel like it was worth the effort to try to deal with that... -- PMM
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 11253051156..311d654cdce 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -809,6 +809,7 @@ static void cortex_r52_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); cpu->midr = 0x411fd133; /* r1p3 */ cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034023;
The Cortex-R52 implements the Configuration Base Address Register (CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU type, so that our implementation provides the register and the associated qdev property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/cpu32.c | 1 + 1 file changed, 1 insertion(+)