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[176.184.26.1]) by smtp.gmail.com with ESMTPSA id i1-20020a05600c354100b0040d8ff79fd8sm1942471wmq.7.2024.01.05.07.45.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 05 Jan 2024 07:45:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Gavin Shan , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Bastian Koppelmann Subject: [PULL 20/71] target/tricore: Use generic cpu_list() Date: Fri, 5 Jan 2024 16:42:13 +0100 Message-ID: <20240105154307.21385-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240105154307.21385-1-philmd@linaro.org> References: <20240105154307.21385-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan No changes in the output from the following command. [gshan@gshan q]$ ./build/qemu-system-tricore -cpu ? Available CPUs: tc1796 tc1797 tc27x tc37x Signed-off-by: Gavin Shan Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231114235628.534334-21-gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- target/tricore/cpu.h | 4 ---- target/tricore/helper.c | 22 ---------------------- 2 files changed, 26 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index de3ab53a83..2d4446cea5 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -246,10 +246,6 @@ void fpu_set_state(CPUTriCoreState *env); #define MMU_USER_IDX 2 -void tricore_cpu_list(void); - -#define cpu_list tricore_cpu_list - static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) { return 0; diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7e5da3cb23..174f666e1e 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -96,28 +96,6 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } } -static void tricore_cpu_list_entry(gpointer data, gpointer user_data) -{ - ObjectClass *oc = data; - const char *typename; - char *name; - - typename = object_class_get_name(oc); - name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU)); - qemu_printf(" %s\n", name); - g_free(name); -} - -void tricore_cpu_list(void) -{ - GSList *list; - - list = object_class_get_list_sorted(TYPE_TRICORE_CPU, false); - qemu_printf("Available CPUs:\n"); - g_slist_foreach(list, tricore_cpu_list_entry, NULL); - g_slist_free(list); -} - void fpu_set_state(CPUTriCoreState *env) { switch (extract32(env->PSW, 24, 2)) {