From patchwork Mon Dec 18 11:32:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755492 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp828805wra; Mon, 18 Dec 2023 03:38:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IFV6PaGGQqOYcGM+fPH8ExLGmLI+ZC3EyfsbPVRbh4KA7uBP2Sgzx06ed4NryEbBo2EW2K5 X-Received: by 2002:a05:620a:45a1:b0:77d:c2ef:9ecf with SMTP id bp33-20020a05620a45a100b0077dc2ef9ecfmr19802693qkb.51.1702899508269; Mon, 18 Dec 2023 03:38:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702899508; cv=none; d=google.com; s=arc-20160816; b=OUcdUWCx+YFORj+UybYJIIaDsq5vnEks75fcNuaLyYSR0QsDZiB3pdhyP+c4AMQ2ym svDgYIKn9ISol9I3s/LWwx5DOwPUpcsjHVwu/i+htViQJCfwskZAGj1rWmoh1FGSomeq 8sFzBaBFOIH+MkS5MYznVVBV5jm6S6fAjJs2laobyCe3qffjhFmudrvZmkw2HmBs4zpw FFoK3NUzSSEZpPzF/EQ4yLxQfOG+UvyA3SLk54TPL8d+SoxtkbCVTryDfSwyPQc1lFgO TqDeB3qNV2oSSDDpU0WG5Dz0FFKNSNvIaB8j7uQ8KOmFmXsNmOGJVMg04STWpPF0HSVY 6lIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XBGAau5xQawMv1TIkYCOIFZhD76YOOoYpu6Y5VQfn/w=; fh=H2AmuqulvQE+T5zu97MCEUC3z9wF9NssS7895NhR/+c=; b=MCce4fMFsI9Im3Oo5neU85pq55Lc4soR14ZTSeUsLBYdiij7THrVfRDzZloPstg3Jq 4rhmrxXucXo4ANJTgXSSmp5KXWHI6RcgDBHf+oJsQxmYx/6nitKr6WiGDuTb+3chUr+2 jNwI7z9HG0K67kPcfDclxR4hg0f9XBlph8p+yGwrE1MkfYeVjoTfD0PB5xrIsK/5vtCg KseVAe4eyHO83hs2r3KbqvR8cwcmrM99iKuMipsKhf+RBiSXycK0qpj1Z5+d8BVYc+OM NLpZk/TJMN/A5KzzWBZUwtLUAAQCx9IqZc+RAe0sa5au3gdLIWm8M0HxETdRwDc1RH2x +6Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p1nx/xiz"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v16-20020a05620a0f1000b00780e1cb1551si3011494qkl.412.2023.12.18.03.38.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2023 03:38:28 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p1nx/xiz"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFBsX-0007ED-7U; Mon, 18 Dec 2023 06:33:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFBsM-00077t-4P for qemu-devel@nongnu.org; Mon, 18 Dec 2023 06:33:35 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFBs5-0003Lj-Vi for qemu-devel@nongnu.org; Mon, 18 Dec 2023 06:33:33 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3365f09de18so1649466f8f.2 for ; Mon, 18 Dec 2023 03:33:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702899196; x=1703503996; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=XBGAau5xQawMv1TIkYCOIFZhD76YOOoYpu6Y5VQfn/w=; b=p1nx/xizLrpkfy5i/rxVvJxdN22v/GAJQne56MBnSRuBZvZOtlKlgmp4NT0TKUnBQn JuqdXo/XhaL82QhWyrStx4rIZkv9SdNo/90lEM2lkluZqhglRLK+25rg1f0vknL8ci6X x68X9dXwgkUNgiRINGOmYrqMI/e3AwRt9J44UnhJoSW+GgP4CcfJHvueR8pTAY13IsJ7 MatwDNAI0Yy/16z6BNtzBSoraupwFANvxKXXszfYMdF3Zf2jzFBb07zFxx9XMklNq9fu z03IJFoPm2LRruqhJRXfiqFyrp8KoPZUz1B+SMGhe/rvFDEJ5PqYbmPYq98nlJa0Tz3T GUhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702899196; x=1703503996; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XBGAau5xQawMv1TIkYCOIFZhD76YOOoYpu6Y5VQfn/w=; b=CFEXyo6/hPNxPjNPaQNthVsvqLr0NQ73h5rmS3Utk/85aTmeKsxwu8sviz4sK/Z+yj fxnXrVOZR3lEvypze+8YhJzjXrqf+aH9IsUhWDOo586IuIKtLES01wcnYcvOLsvtlFIf vnmQHUi39smPOBND8ktJQ3zWFtElAqA+8kNsZGomuA3aLr1yeAEPdDjfYhNEV+4hvIYx 5y5qwken+KUDgWd7LPwM0kVkJeUvjErOWoRdUqy9LXJajVjyiz+9BO36/14u3NQ+y1qC ho1+sFvKMGMO+jAjfoyFrTgHbON0+1uT2PyDd2AYgqBqmxPXeT1587BhSBBvO/MIo7x4 Zf9w== X-Gm-Message-State: AOJu0YxvLVfSrIDtorkD1Mp4RrUaWU8y5c+rfbmJzQwyHdaW+uael1QW ZJfEpjbkZf1wZfoOLYHNt92yhA== X-Received: by 2002:adf:e2c2:0:b0:332:eaa7:56b0 with SMTP id d2-20020adfe2c2000000b00332eaa756b0mr7873228wrj.14.1702899196728; Mon, 18 Dec 2023 03:33:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j18-20020adff012000000b003366da509ecsm671193wro.85.2023.12.18.03.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 03:33:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/35] target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs Date: Mon, 18 Dec 2023 11:32:51 +0000 Message-Id: <20231218113305.2511480-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113305.2511480-1-peter.maydell@linaro.org> References: <20231218113305.2511480-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2 support to FEAT_NV for the latter two CPU types. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 8 +++++--- target/arm/tcg/cpu64.c | 1 + 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0b604f90059..d827b42de79 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -63,6 +63,7 @@ the following architecture extensions: - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) +- FEAT_NV (Nested Virtualization) - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) - FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm) - FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index efb22a87f9e..da0c02f850b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2238,9 +2238,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); - /* FEAT_NV (Nested Virtualization) */ - cpu->isar.id_aa64mmfr2 = - FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); + /* FEAT_NV2 (Enhanced Nested Virtualization support) */ + if (FIELD_EX64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV) > 1) { + cpu->isar.id_aa64mmfr2 = + FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 1); + } } /* MPU can be configured out of a PMSA CPU either by setting has-mpu diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 40e7a45166f..93f040e6e96 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1204,6 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t = FIELD_DP64(t, ID_AA64MMFR2, NV, 1); /* FEAT_NV */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */