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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 17/33] hw/cpu/arm: Document more properties of CORTEX_MPCORE_PRIV QOM type Date: Tue, 12 Dec 2023 17:29:17 +0100 Message-ID: <20231212162935.42910-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=philmd@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- include/hw/cpu/cortex_mpcore.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/hw/cpu/cortex_mpcore.h b/include/hw/cpu/cortex_mpcore.h index 4697fd47c7..73627bc415 100644 --- a/include/hw/cpu/cortex_mpcore.h +++ b/include/hw/cpu/cortex_mpcore.h @@ -28,10 +28,17 @@ * some timers and watchdogs * * QEMU interface: + * + QOM property "cluster-id" which set the cluster ID and its affinity. * + QOM property "num-cores" which set the number of cores present in * the cluster. + * + QOM property "cpu-type" is the CPU model typename. * + QOM properties "cpu-has-el3", "cpu-has-el2" which set whether the CPUs * have the exception level features present. + * + QOM properties "cpu-has-vfp-d32", "cpu-has-neon" which set whether the + * CPUs have the FPU features present. + * + QOM property "cpu-freq-hz" is the frequency of each core + * + QOM property "cpu-memory" is a MemoryRegion containing the devices + * provided by the board model. * + QOM property "gic-spi-num" sets the number of GIC Shared Peripheral * Interrupts. * QEMU interface forwarded from the GIC: