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Mon, 11 Dec 2023 01:20:57 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 6A3EC5FBF8; Mon, 11 Dec 2023 09:13:47 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: John Snow , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Wainer dos Santos Moschetta , Cleber Rosa , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Beraldo Leal , Richard Henderson , Pavel Dovgalyuk , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v2 15/16] accel/tcg: add trace_tlb_resize trace point Date: Mon, 11 Dec 2023 09:13:44 +0000 Message-Id: <20231211091346.14616-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231211091346.14616-1-alex.bennee@linaro.org> References: <20231211091346.14616-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org I wondered if the discrepancy I was seeing in fill patterns was due to some sort of non-deterministic resize being triggered. In theory we could resize away at any point which might account for the difference. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 2 ++ accel/tcg/trace-events | 1 + 2 files changed, 3 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c35df27caf..63f2a23709 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -201,6 +201,8 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast, return; } + trace_tlb_resize(old_size, new_size); + g_free(fast->table); g_free(desc->fulltlb); diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events index 31dda01c12..11b49a63f1 100644 --- a/accel/tcg/trace-events +++ b/accel/tcg/trace-events @@ -10,6 +10,7 @@ exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p flags=0x%x" memory_notdirty_write_access(uint64_t vaddr, uint64_t ram_addr, unsigned size) "0x%" PRIx64 " ram_addr 0x%" PRIx64 " size %u" memory_notdirty_set_dirty(uint64_t vaddr) "0x%" PRIx64 tlb_fill(uint64_t vaddr, int size, int access_type, int mmu_idx) "0x%" PRIx64 "/%d %d %d" +tlb_resize(size_t old, size_t new) "%zu -> %zu" # translate-all.c translate_block(void *tb, uintptr_t pc, const void *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p"