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[209.51.188.17]) by mx.google.com with ESMTPS id i21-20020a05620a145500b0077d7d37d036si9087553qkl.687.2023.12.04.07.26.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Dec 2023 07:26:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MB/sBipi"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rAApx-000450-Hs; Mon, 04 Dec 2023 10:26:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rAApp-00042I-0A for qemu-devel@nongnu.org; Mon, 04 Dec 2023 10:26:13 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rAApm-0005T5-6T for qemu-devel@nongnu.org; Mon, 04 Dec 2023 10:26:12 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40c0a074e71so12517235e9.1 for ; Mon, 04 Dec 2023 07:26:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701703568; x=1702308368; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hwIlmu7y+8erPdoR/Kkd+7013w7hW587KwHOvMnbXVw=; b=MB/sBipiwkb23i9jGyz/FuzYzwo/tL9DvMx8tI32jrTb1hZbXDKQBKGT49F+B84bRw TNndYFi6jP1HjOHggS/8eEvinRohZZ8pWwjBjhrNT48HwqYl3rwuK0VliMh5+Sk+npK+ R+W+nbbdF4QDFcXPPIuSLnYM407qA2HPrlGW7amMpwdTNOCuLbZGNZIyG8ijvHzTh4KE IygEVVjkHodQVjwZJF0YFoBsfsysLk8dq10Sn+0Uqmf2r7bl/41pit2mk/6IqJsIdy/o 6zSTWiJRdsNx9Bg2wcBzhqFDTKPzu7ZlKJxK4E4LwmSlnrA8QeICKXDRYC/vkmvsHZs/ bsbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701703568; x=1702308368; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hwIlmu7y+8erPdoR/Kkd+7013w7hW587KwHOvMnbXVw=; b=xA/PlvLAnkJj7kkZe/FlHtaUnkwyLLQWJcpnU9Xz9ylXITUOcEq6Ju1jgrXHKpFXQe 8O0o1MAX2pczghB/eicpoT0oPfOdb7j+G3ySqG7LaZuxjZI7LOvFBPFLbmsvbe5hIu8x 1fjKDaNAI0U9G6XtjOBgn8CIGnEedPBYRK28PHJ/I1dQAaNx6aiYPr4jqh4izxJRt7HU 3mhBQzZclLnl1A2aSUofxEnFmhbbW3LEr8CJPycYwF1HKL8SgX5rEqld30POkcIj6QQ7 IDKZZbou6Roots4J8YMQY5kE++58Umr5vm6mJQDUwYyo3dKmjMXMnr2dlx5deE+x4ptm 7xQg== X-Gm-Message-State: AOJu0Yz3eI+tcOkfStu5D2HQwqrAO/uIdzdr830Eh8EEm3EUOhq9J2TZ 3Koz9/uJBRoai5vZXrUOYC4PwEhlpZjlLHPAYQM= X-Received: by 2002:a05:600c:354f:b0:40b:3645:4671 with SMTP id i15-20020a05600c354f00b0040b36454671mr3949699wmq.10.1701703568398; Mon, 04 Dec 2023 07:26:08 -0800 (PST) Received: from m1x-phil.lan ([176.176.140.35]) by smtp.gmail.com with ESMTPSA id r21-20020a05600c35d500b0040b3e79bad3sm15354298wmq.40.2023.12.04.07.26.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 04 Dec 2023 07:26:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Alistair Francis , Palmer Dabbelt , Bin Meng , Weiwei Li , Liu Zhiwei Subject: [PULL 2/4] target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csr Date: Mon, 4 Dec 2023 16:25:22 +0100 Message-ID: <20231204152524.37803-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231204152524.37803-1-philmd@linaro.org> References: <20231204152524.37803-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Daniel Henrique Barboza KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() use an 'int ret' variable that is used to do an early 'return' if ret > 0. Both are being called in functions that are also declaring a 'ret' integer, initialized with '0', and this integer is used as return of the function. The result is that the compiler is less than pleased and is pointing shadowing errors: ../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_get_regs_csr': ../target/riscv/kvm/kvm-cpu.c:90:13: error: declaration of 'ret' shadows a previous local [-Werror=shadow=compatible-local] 90 | int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ | ^~~ ../target/riscv/kvm/kvm-cpu.c:539:5: note: in expansion of macro 'KVM_RISCV_GET_CSR' 539 | KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); | ^~~~~~~~~~~~~~~~~ ../target/riscv/kvm/kvm-cpu.c:536:9: note: shadowed declaration is here 536 | int ret = 0; | ^~~ ../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_put_regs_csr': ../target/riscv/kvm/kvm-cpu.c:98:13: error: declaration of 'ret' shadows a previous local [-Werror=shadow=compatible-local] 98 | int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ | ^~~ ../target/riscv/kvm/kvm-cpu.c:556:5: note: in expansion of macro 'KVM_RISCV_SET_CSR' 556 | KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); | ^~~~~~~~~~~~~~~~~ ../target/riscv/kvm/kvm-cpu.c:553:9: note: shadowed declaration is here 553 | int ret = 0; | ^~~ The macros are doing early returns for non-zero returns and the local 'ret' variable for both functions is used just to do 'return 0', so remove them from kvm_riscv_get_regs_csr() and kvm_riscv_put_regs_csr() and do a straight 'return 0' in the end. For good measure let's also rename the 'ret' variables in KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() to '_ret' to make them more resilient to these kind of errors. Fixes: 937f0b4512 ("target/riscv: Implement kvm_arch_get_registers") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20231123101338.1040134-1-dbarboza@ventanamicro.com> Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/kvm/kvm-cpu.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 78fa1fa162..45b6cf1cfa 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -87,17 +87,17 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ do { \ - int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ - if (ret) { \ - return ret; \ + int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + if (_ret) { \ + return _ret; \ } \ } while (0) #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ do { \ - int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ - if (ret) { \ - return ret; \ + int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + if (_ret) { \ + return _ret; \ } \ } while (0) @@ -533,7 +533,6 @@ static int kvm_riscv_put_regs_core(CPUState *cs) static int kvm_riscv_get_regs_csr(CPUState *cs) { - int ret = 0; CPURISCVState *env = &RISCV_CPU(cs)->env; KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); @@ -545,12 +544,12 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) KVM_RISCV_GET_CSR(cs, env, stval, env->stval); KVM_RISCV_GET_CSR(cs, env, sip, env->mip); KVM_RISCV_GET_CSR(cs, env, satp, env->satp); - return ret; + + return 0; } static int kvm_riscv_put_regs_csr(CPUState *cs) { - int ret = 0; CPURISCVState *env = &RISCV_CPU(cs)->env; KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); @@ -563,7 +562,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) KVM_RISCV_SET_CSR(cs, env, sip, env->mip); KVM_RISCV_SET_CSR(cs, env, satp, env->satp); - return ret; + return 0; } static int kvm_riscv_get_regs_fp(CPUState *cs)