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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id t3-20020a5d6903000000b0032da49e18fasm66146wru.23.2023.11.22.10.31.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH-for-9.0 05/11] target/arm: Move GTIMER definitions to 'cpu-defs.h' Date: Wed, 22 Nov 2023 19:30:41 +0100 Message-ID: <20231122183048.17150-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org To allow GTIMER_* definitions to be used by non-ARM specific hardware models, move them to a new target agnostic "cpu-defs.h" header. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu-defs.h | 19 +++++++++++++++++++ target/arm/cpu.h | 8 +------- hw/arm/bcm2836.c | 1 + 3 files changed, 21 insertions(+), 7 deletions(-) create mode 100644 target/arm/cpu-defs.h diff --git a/target/arm/cpu-defs.h b/target/arm/cpu-defs.h new file mode 100644 index 0000000000..1ad76aff14 --- /dev/null +++ b/target/arm/cpu-defs.h @@ -0,0 +1,19 @@ +/* + * ARM "target agnostic" CPU definitions + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ARM_CPU_DEFS_H +#define ARM_CPU_DEFS_H + +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 + +#endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 124d829742..8107e4d446 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -24,6 +24,7 @@ #include "qemu/cpu-float.h" #include "hw/registerfields.h" #include "cpu-qom.h" +#include "target/arm/cpu-defs.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" @@ -154,13 +155,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define GTIMER_HYPVIRT 4 -#define NUM_GTIMERS 5 - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 166dc896c0..6986b71cb4 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -15,6 +15,7 @@ #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" +#include "target/arm/cpu-defs.h" struct BCM283XClass { /*< private >*/