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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id f3-20020a05600c43c300b003fc0505be19sm176312wmn.37.2023.11.22.10.31.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 02/11] target/arm: Add target_aarch64_available() helper Date: Wed, 22 Nov 2023 19:30:38 +0100 Message-ID: <20231122183048.17150-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We want to build HW models once, but don't want to register types when all prerequisites are satisfied. Add the target_aarch64_available() to know at runtime whether TARGET_AARCH64 is built-in. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu-qom.h | 2 ++ target/arm/cpu.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 02b914c876..bf6b3604ed 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,4 +33,6 @@ typedef struct AArch64CPUClass AArch64CPUClass; DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) +bool target_aarch64_available(void); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 25e9d2ae7b..1990c04089 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2548,3 +2548,12 @@ static void arm_cpu_register_types(void) } type_init(arm_cpu_register_types) + +bool target_aarch64_available(void) +{ +#ifdef TARGET_AARCH64 + return true; +#else + return false; +#endif +}