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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id d11-20020adfa40b000000b003232380ffd7sm38237wra.102.2023.11.22.10.31.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 11/11] hw/intc/meson: Simplify how arm_gicv3_kvm.o objects are built Date: Wed, 22 Nov 2023 19:30:47 +0100 Message-ID: <20231122183048.17150-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the target_aarch64_available() to build the ARM_GIC_KVM types regardless the ARM/AARCH64 targets are selected, but restrict its registration to TARGET_AARCH64 presence at runtime. This will help to have a single binary running both ARM/Aarch64. Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/arm_gicv3_its_kvm.c | 1 + hw/intc/arm_gicv3_kvm.c | 1 + hw/intc/meson.build | 6 ++++-- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index f7df602cff..b3063c4cd7 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -261,6 +261,7 @@ static const TypeInfo kvm_arm_its_info = { .instance_size = sizeof(GICv3ITSState), .class_init = kvm_arm_its_class_init, .class_size = sizeof(KVMARMITSClass), + .can_register = target_aarch64_available, }; static void kvm_arm_its_register_types(void) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 77eb37e131..33321dee5d 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -909,6 +909,7 @@ static const TypeInfo kvm_arm_gicv3_info = { .instance_size = sizeof(GICv3State), .class_init = kvm_arm_gicv3_class_init, .class_size = sizeof(KVMARMGICv3Class), + .can_register = target_aarch64_available, }; static void kvm_arm_gicv3_register_types(void) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index ed355941d1..d45eb76f36 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -40,8 +40,10 @@ endif specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cpuif.c')) -specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) -specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files( + 'arm_gic_kvm.c', + 'arm_gicv3_kvm.c', + 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))