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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id b5-20020a05600c4e0500b003feae747ff2sm261799wmq.35.2023.11.22.10.31.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 09/11] hw/arm/bcm2836: Allocate ARM CPU state with object_new() Date: Wed, 22 Nov 2023 19:30:45 +0100 Message-ID: <20231122183048.17150-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ARMCPU type is forward declared as a pointer to all hw/ files. Its declaration is restricted to target/arm/ files. By using a pointer in BCM283XState instead of embedding the whole CPU state, we don't need to include "cpu.h" which is target-specific. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/arm/bcm2836.h | 4 ++-- hw/arm/bcm2836.c | 19 ++++++++++--------- hw/arm/raspi.c | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 6f90cabfa3..784bab0aad 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -14,7 +14,7 @@ #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" -#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" #include "qom/object.h" #define TYPE_BCM283X "bcm283x" @@ -38,7 +38,7 @@ struct BCM283XState { uint32_t enabled_cpus; struct { - ARMCPU core; + ARMCPU *core; } cpu[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 8031a74600..4f5acee77e 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -39,8 +39,9 @@ static void bcm2836_init(Object *obj) int n; for (n = 0; n < bc->core_count; n++) { - object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, - bc->cpu_type); + s->cpu[n].core = ARM_CPU(object_new(bc->cpu_type)); + object_property_add_child(obj, "cpu[*]", OBJECT(s->cpu[n].core)); + qdev_realize_and_unref(DEVICE(s->cpu[n].core), NULL, &error_abort); } if (bc->core_count > 1) { qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); @@ -139,24 +140,24 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off", n >= s->enabled_cpus, &error_abort); - if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { + if (!qdev_realize(DEVICE(s->cpu[n].core), NULL, errp)) { return; } /* Connect irq/fiq outputs from the interrupt controller. */ qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(s->cpu[n].core), ARM_CPU_IRQ)); qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(s->cpu[n].core), ARM_CPU_FIQ)); /* Connect timers from the CPU to the interrupt controller */ - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_PHYS, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_VIRT, qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_HYP, qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); } } diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index cc4c4ec9bf..01c391b90a 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -252,7 +252,7 @@ static void setup_boot(MachineState *machine, RaspiProcessorId processor_id, s->binfo.firmware_loaded = true; } - arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo); + arm_load_kernel(s->soc.cpu[0].core, machine, &s->binfo); } static void raspi_machine_init(MachineState *machine)