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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id e6-20020a170902d38600b001c731b62403sm4271910pld.218.2023.11.13.09.32.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 09:32:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 01/12] target/hppa: Mask reserved PSW bits in expand_sm_imm Date: Mon, 13 Nov 2023 09:32:26 -0800 Message-Id: <20231113173237.48233-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231113173237.48233-1-richard.henderson@linaro.org> References: <20231113173237.48233-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Helge Deller The system mask is a restricted subset of the psw, with only a couple of reserved bits. It is better to handle this up front in the translator than require helper_swap_system_mask to use cpu_hppa_get_psw and cpu_hppa_put_psw. Signed-off-by: Helge Deller [rth: Handle this in expand_sm_imm not helper_swap_system_mask.] Signed-off-by: Richard Henderson --- target/hppa/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index bcce65d587..f3b17ba16d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -77,11 +77,14 @@ typedef struct DisasContext { /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { - if (val & PSW_SM_E) { - val = (val & ~PSW_SM_E) | PSW_E; - } - if (val & PSW_SM_W) { - val = (val & ~PSW_SM_W) | PSW_W; + /* Keep unimplemented bits disabled -- see cpu_hppa_put_psw. */ + if (ctx->is_pa20) { + if (val & PSW_SM_W) { + val |= PSW_W; + } + val &= ~(PSW_SM_W | PSW_SM_E | PSW_G); + } else { + val &= ~(PSW_SM_W | PSW_SM_E | PSW_O); } return val; }