From patchwork Tue Nov 7 03:03:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 741798 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1419766wrr; Mon, 6 Nov 2023 19:07:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IHguvdkybYyVtPOLjcBYvsGp9ZOxubIXDHwRe7qERYEyGtv/plegT8RdwN+/7KGgna2sesd X-Received: by 2002:a05:620a:8a12:b0:775:aaf7:903f with SMTP id qt18-20020a05620a8a1200b00775aaf7903fmr26085066qkn.67.1699326436680; Mon, 06 Nov 2023 19:07:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699326436; cv=none; d=google.com; s=arc-20160816; b=tSGn7qCQ+CZG9DnytUgsiM7geFGDSrl1CNOa+r+T9YZYQMf23bgINWxGtzSuzQSuoN km13KhZHz5veTvy3ofZcv2mvqnIZDekLL4j2IN0NDjlcudf46DxF9Hi9yeUVQovSG9RR sK9s9muvPdAvHTsVq1Hid5mRCrJpsrr8VP9Mdw11MYJv5puxTGFmwEYihzT6H2KMvVja j+F1Yp1/zHTE7fq7wvKNGtBbk4MdRp5hTfmQP0w73x5F7ZrJqpqAvi6pXws4TUgn51vk 1Ar2w9woNlK0wa4goovlnO7rqI1WfzWlPP9eMb8RC3e/pRidH9V8EXiHhLi6iGVa4huK IeXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I/ED2o2s4ms+vsY/bEE/bt2PcFzZktCazvwqho7s/dw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=g5Sxdd9eH6WwGlFFHUuW3g2WyIvLLEjE5M0zVJuaWhZuVPKJtHaXgiATuOZ40AyALW c7KTkF7wJAyN6AhKguvXocHtb8M6c1TIIj9xYJd/T5DQE2ZV9PeNKOWeqcg8v/wwXMTB FX/MwZ2P/H2aHnjRykTSoeVWKbhZvEePjDp6Z4j9hspU5XSSVmEe8yY+3qeDTKVXDxdM vm+wbeLtdqDKDU7bM/4epqsfcwBeuQ2xe04unHUNlHNJs6Q50zyWTz6zezVXomCTkbKL d/nMoU04Ca1vp0q9Wi1psgEwI4oWYt+UydDdM/t9mD2THWFX2/8IFC4qD/xRHMvpoI8G 9Ciw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DxA5jnop; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id qc10-20020a05620a654a00b00778b115b7b4si5841093qkn.440.2023.11.06.19.07.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Nov 2023 19:07:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DxA5jnop; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r0CPN-0000SL-K8; Mon, 06 Nov 2023 22:05:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0COb-0007Mz-Vt for qemu-devel@nongnu.org; Mon, 06 Nov 2023 22:04:54 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r0COL-0000gQ-4m for qemu-devel@nongnu.org; Mon, 06 Nov 2023 22:04:53 -0500 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1cc2575dfc7so37448555ad.1 for ; Mon, 06 Nov 2023 19:04:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699326266; x=1699931066; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=I/ED2o2s4ms+vsY/bEE/bt2PcFzZktCazvwqho7s/dw=; b=DxA5jnopCJE0xi3vlalJGtwjq85HGbX1Z8HWxtb7IDU4cfCIXWTXrgwGq5LetAw+qa 7JPMt/sM5OzOAy+lYfAJrQ0Cf/Yv8/Nw6AZv1YHKTaTC75VSt+yxugzCZ+V9LNCw5MZB tJ/YPe+9lMNPRzqwic19WDx1w5SWkr2RRpVgOV5qI0R2a8wC8CBVcxkOLvYBY7BtDZoE uvLsLNi1WbMJ4LBlL5rpyoOt3d2Sy3FoQGxN6kQT7jEqHt5lWTaiaYrQz9UWrgHvqr5M 2s3r5Z0mmXV/MFFMGlKzm+IBygc1Wtl4YEemld1oZY83oA2ihJA7cjDBr0hMdNf6Ms9I c3dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699326266; x=1699931066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I/ED2o2s4ms+vsY/bEE/bt2PcFzZktCazvwqho7s/dw=; b=Yb+ciRERdwHZDIE+uzJwaied4ZAJqGp7eaOJC8DD39nh87d3M5YP8QNTswIZi8Fh0x 3guB15fUv2nnIAJJpGZ9AkEAzbNP4Chq4JJJUQoeBUFoMaxPfyA2pSeO2jyN8OATIva3 lEpGgcs6vEjto3A5AX25d+NyR5Y68QOAXTmNMR82jaXEoZKE3a0Ak5ZnXhsLyjwqiQha kI4SBjM0toI6LlIF/M1xgvnYyHWvFrEDemNrF339P3yVx907KD+CKh1R17/4hi15iO3k YyyDaAoDQHS9FeYP7JqE2/2ic/ZWwkdNVDZibD4TYYKAxl040rFKbAc57Cu3XxT0rqIp 3EdQ== X-Gm-Message-State: AOJu0YyaaesTGLlMcldeLYRrIQlIIlYsuNZDltYFFaU56gUdiNoX2NUF Vo+jdgMx0g54uG3xEXWpwC2Yg/W2n9PUogO76/M= X-Received: by 2002:a17:902:bc42:b0:1ca:87e0:93e3 with SMTP id t2-20020a170902bc4200b001ca87e093e3mr26242032plz.7.1699326266461; Mon, 06 Nov 2023 19:04:26 -0800 (PST) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u9-20020a17090282c900b001c72d5e16acsm6518012plz.57.2023.11.06.19.04.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 19:04:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 24/85] target/hppa: Fix hppa64 addressing Date: Mon, 6 Nov 2023 19:03:06 -0800 Message-Id: <20231107030407.8979-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231107030407.8979-1-richard.henderson@linaro.org> References: <20231107030407.8979-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 7 +++---- target/hppa/translate.c | 22 +++++++++++++--------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 2999df9ff9..cb838defb0 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -302,7 +302,7 @@ static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, #ifdef CONFIG_USER_ONLY return off; #else - off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); + off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32); return spc | off; #endif } @@ -343,9 +343,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - *pc = (env->psw & PSW_C - ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) - : env->iaoq_f & -4); + *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); *cs_base = env->iasq_f; /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 44c9911720..4e0bc48b09 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -710,6 +710,13 @@ static bool nullify_end(DisasContext *ctx) return true; } +static target_ureg gva_offset_mask(DisasContext *ctx) +{ + return (ctx->tb_flags & PSW_W + ? MAKE_64BIT_MASK(0, 62) + : MAKE_64BIT_MASK(0, 32)); +} + static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) { if (unlikely(ival == -1)) { @@ -1398,7 +1405,8 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) tmp = tcg_temp_new(); spc = tcg_temp_new_tl(); - tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); + /* Extract top 2 bits of the address, shift left 3 for uint64_t index. */ + tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_trunc_reg_ptr(ptr, tmp); @@ -1415,6 +1423,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, { TCGv_reg base = load_gpr(ctx, rb); TCGv_reg ofs; + TCGv_tl addr; /* Note that RX is mutually exclusive with DISP. */ if (rx) { @@ -1429,18 +1438,13 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, } *pofs = ofs; -#ifdef CONFIG_USER_ONLY - *pgva = (modify <= 0 ? ofs : base); -#else - TCGv_tl addr = tcg_temp_new_tl(); + *pgva = addr = tcg_temp_new_tl(); tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); - if (ctx->tb_flags & PSW_W) { - tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); - } + tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); +#ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); } - *pgva = addr; #endif }