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[PULL,12/85] target/hppa: Truncate rotate count in trans_shrpw_sar

Message ID 20231107030407.8979-13-richard.henderson@linaro.org
State Accepted
Commit e1d635e871f4e0dcea7ec08309509bbb82c2047c
Headers show
Series [PULL,01/85] target/hppa: Include PSW_P in tb flags and mmu index | expand

Commit Message

Richard Henderson Nov. 7, 2023, 3:02 a.m. UTC 
When forcing rotate by i32, the shift count must be as well.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 20e44ed528..d6ccce020a 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3105,8 +3105,11 @@  static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
         tcg_gen_shr_reg(dest, dest, cpu_sar);
     } else if (a->r1 == a->r2) {
         TCGv_i32 t32 = tcg_temp_new_i32();
+        TCGv_i32 s32 = tcg_temp_new_i32();
+
         tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2));
-        tcg_gen_rotr_i32(t32, t32, cpu_sar);
+        tcg_gen_trunc_reg_i32(s32, cpu_sar);
+        tcg_gen_rotr_i32(t32, t32, s32);
         tcg_gen_extu_i32_reg(dest, t32);
     } else {
         TCGv_i64 t = tcg_temp_new_i64();